library ieee; 
use ieee.std_logic_1164.all; 

entity rtl_buffer is
	port
	(
		clock              : in     std_logic;
		data_buffer        : buffer std_logic := '0'
	);
end rtl_buffer;

architecture rtl of rtl_buffer is

begin

process begin
	wait until rising_edge(clock);
	data_buffer <= not data_buffer;
end process;

end;