library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity rtl_inout is
	port
	(
		clock              : in    std_logic;
		data_inout         : inout std_logic
	);
end rtl_inout;

architecture rtl of rtl_inout is

signal counter             : unsigned(1 downto 0) := "00";
signal data_in             : std_logic := '0';

begin

data_inout <= counter(0) when counter(1) = '1' else 'Z';

process begin
	wait until rising_edge(clock);
	data_in <= data_inout;
	counter <= counter + 1;
end process;

end;