library ieee; 
use ieee.std_logic_1164.all; 

entity rtl_out_vhdl2008 is
	port
	(
		clock              : in  std_logic;
		data_out_vhdl2008  : out std_logic := '0'
	);
end rtl_out_vhdl2008;

architecture rtl of rtl_out_vhdl2008 is

begin

process begin
	wait until rising_edge(clock);
	data_out_vhdl2008 <= not data_out_vhdl2008;
end process;

end;