library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity tb_buffer_inout_out_vhdl2008 is
end tb_buffer_inout_out_vhdl2008;

architecture tb of tb_buffer_inout_out_vhdl2008 is

component rtl_inout is
	port
	(
		clock              : in     std_logic;
		data_inout         : inout  std_logic
	);
end component;

component rtl_buffer is
	port
	(
		clock              : in     std_logic;
		data_buffer        : buffer std_logic
	);
end component;

component rtl_out_vhdl2008 is
	port
	(
		clock              : in     std_logic;
		data_out_vhdl2008  : out    std_logic
	);
end component;

signal clock               : std_logic := '1';
signal data_inout          : std_logic := '0';
signal data_buffer         : std_logic := '0';
signal data_out_vhdl2008   : std_logic := '0';

begin

clock <= not clock after 5 ns;

process begin
	data_inout <= 'Z';
	wait for 42.25 ns;
	data_inout <= '1';
	wait for 5 ns;
	data_inout <= '0';
	wait for 5 ns;
	data_inout <= 'Z';
	wait;
end process;

inst_rtl_inout : rtl_inout
	port map
	(
		clock              => clock,
		data_inout         => data_inout
	);

inst_rtl_buffer : rtl_buffer
	port map
	(
		clock              => clock,
		data_buffer        => data_buffer
	);

inst_rtl_out_vhdl2008 : rtl_out_vhdl2008
	port map
	(
		clock              => clock,
		data_out_vhdl2008  => data_out_vhdl2008
	);

end;