LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CNT2 is
	Port(
	clk            : in  std_logic;
	reset          : in  std_logic;
	SW             : in  std_logic;
	SW2            : in  std_logic;
	LED            : out std_logic_vector(1 downto 0) := "00"; --rot/grün leuchtet zu Beginn
	LED2           : out std_logic := '1'; --blau LED
	count2         : out std_logic_vector(31 downto 0); --integer :=0;
	wren           : out std_logic := '1';
	wren4          : out std_logic_vector(3 downto 0) := "1111";
	clock_out      : out std_logic; --langsame Clock
	addra          : out std_logic_vector(31 downto 0));
end CNT2;

architecture Behavioral of CNT2 is

signal limit       : integer := 0;
signal cnt         : integer RANGE 0 TO 5201 := 0; --Integer hat range von 32 Bit, durch angabe von extra range wird dieser angepasst
signal count       : integer := 1;
signal tmp         : std_logic := '0';
signal addrcnt     : integer RANGE 0 TO 40801 := 0; --TO 257 := 0;

begin

process(clk, reset, SW)
begin
	if reset = '1' or SW = '1' then
		count <= 1;
		LED   <= "01"; --rot bleibt an also ist rot LED[01] 0 an höchstem Bit
		tmp   <= '0';
	elsif clk'event and clk = '1' then
		LED2  <= SW2;
		count <= count + 1;
		if cnt = 5000 then --Aufhören zum zählen
			addrcnt <= 0;
			count2  <= conv_std_logic_vector(0,32);
			addra   <= conv_std_logic_vector(0,32);
			wren    <= '0';
		else
			if count = 125 then
				tmp     <= NOT tmp;
				cnt     <= cnt + 1;
				addrcnt <= addrcnt + 4;
			elsif count = 250 then
				tmp     <= NOT tmp;
				addra   <= conv_std_logic_vector(addrcnt,32);
				count2  <= conv_std_logic_vector(cnt,32);
				count   <= 1;
			end if;
		end if;
	end if;

	clock_out <= tmp;
end process;

end Behavioral;