LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity tb_CNT2 is
end tb_CNT2;

architecture tb of tb_CNT2 is

signal clk         : std_logic := '0';
signal reset       : std_logic := '1';
signal SW          : std_logic := '0';
signal SW2         : std_logic := '0';
signal LED         : std_logic_vector(1 downto 0) := "00";
signal LED2        : std_logic := '0';
signal count2      : std_logic_vector(31 downto 0) := (others => '0');
signal wren        : std_logic := '0';
signal wren4       : std_logic_vector(3 downto 0) := "0000";
signal clock_out   : std_logic := '0';
signal addra       : std_logic_vector(31 downto 0) := (others => '0');

begin

clk <= not clk after 5 ns;

process begin
	wait for 100 ns;
	reset <= '0';
	wait;
end process;

inst_CNT2 : entity work.CNT2
	Port map(
	clk            => clk,
	reset          => reset,
	SW             => SW,
	SW2            => SW2,
	LED            => LED,
	LED2           => LED2,
	count2         => count2,
	wren           => wren,
	wren4          => wren4,
	clock_out      => clock_out,
	addra          => addra);

end;