Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2018833
date_generatedFri Apr 22 17:08:24 2022 os_platformWIN64
product_versionVivado v2017.3 (64-bit) project_idc0841182c3fc427cafb9c01ede958f02
project_iteration1 random_id1e2f93f8-0674-4d94-b60c-fa2d28615334
registration_id1e2f93f8-0674-4d94-b60c-fa2d28615334 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-3930K CPU @ 3.20GHz cpu_speed3202 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
addresstreetablepanel_address_tree_table=2 addsrcwizard_specify_hdl_netlist_block_design=1 addsrcwizard_specify_or_create_constraint_files=1 basedialog_cancel=4
basedialog_ok=22 basedialog_yes=1 cmdmsgdialog_ok=5 coretreetablepanel_core_tree_table=6
createconstraintsfilepanel_file_name=1 createsrcfiledialog_file_name=4 filesetpanel_file_set_panel_tree=32 flownavigatortreepanel_flow_navigator_tree=19
graphicalview_zoom_in=10 graphicalview_zoom_out=16 mainmenumgr_file=2 mainmenumgr_open_recent_project=2
packagetreepanel_package_tree_panel=1 pacommandnames_add_module_to_bd=1 pacommandnames_add_sources=5 pacommandnames_auto_connect_ports=5
pacommandnames_auto_update_hier=1 pacommandnames_create_top_hdl=1 pacommandnames_goto_netlist_design=1 pacommandnames_move_to_design_set=1
pacommandnames_regenerate_layout=1 pacommandnames_save_design=1 pacommandnames_save_rsb_design=2 pacommandnames_simulation_live_run=6
pacommandnames_simulation_run_behavioral=2 pacommandnames_validate_rsb_design=3 pacommandnames_zoom_fit=1 pacommandnames_zoom_out=1
rdicommands_delete=4 rdicommands_save_file=2 rsbapplyautomationbar_run_block_automation=1 rsbapplyautomationbar_run_connection_automation=1
saveprojectutils_save=2 selectmenu_highlight=2 signaltreepanel_signal_tree_table=21 srcchooserpanel_create_file=5
srcmenu_ip_hierarchy=1 syntheticagettingstartedview_recent_projects=1 systembuilderview_add_ip=3 waveformnametree_waveform_name_tree=3
java_command_handlers
addmoduletoblockdesign=1 addsources=4 autoconnectport=5 createblockdesign=2
createtophdl=1 customizersbblock=2 editdelete=4 movetodesignset=1
openblockdesign=1 regeneratersblayout=1 runbitgen=1 runsynthesis=2
savedesign=1 saversbdesign=2 simulationrun=2 simulationrunfortime=6
validatersbdesign=3 viewtaskprojectmanager=1 viewtasksynthesis=3 zoomfit=1
zoomout=1
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=2 simulator_language=Mixed srcsetcount=3 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=7 totalsynthesisruns=7

unisim_transformation
post_unisim_transformation
bibuf=130 bufg=2 carry4=21 fdce=32
fdpe=1 fdre=3308 fdse=333 gnd=347
ibuf=2 ldce=1 lut1=170 lut2=691
lut3=178 lut4=1128 lut5=270 lut6=1358
muxf7=258 obuf=3 ps7=1 ramb36e1=128
ramd32=192 rams32=64 srl16e=259 srlc32e=132
vcc=341
pre_unisim_transformation
bibuf=130 bufg=2 carry4=21 fdce=32
fdpe=1 fdre=3308 fdse=333 gnd=347
ibuf=2 ldce=1 lut1=170 lut2=691
lut3=178 lut4=1128 lut5=270 lut6=1358
muxf7=258 obuf=3 ps7=1 ram32m=32
ramb36e1=128 srl16e=259 srlc32e=132 vcc=341

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=32 bram_ports_newly_gated=0 bram_ports_total=32 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=2036 srls_augmented=0
srls_newly_gated=0 srls_total=166

ip_statistics
CNT2/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VHDL
x_iplibrary=module_ref x_ipname=CNT2 x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
IP_Integrator/1
bdsource=SBD core_container=NA iptotal=1 maxhierdepth=1
numblks=17 numhdlrefblks=0 numhierblks=4 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=13 numsysgenblks=0
synth_mode=Global x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=bd_afc3
x_ipvendor=xilinx.com x_ipversion=1.00.a
IP_Integrator/2
bdsource=USER core_container=NA da_axi4_cnt=1 da_ps7_cnt=1
iptotal=1 maxhierdepth=0 numblks=6 numhdlrefblks=1
numhierblks=0 numhlsblks=0 numnonxlnxblks=0 numpkgbdblks=0
numreposblks=6 numsysgenblks=0 synth_mode=OOC_per_IP x_iplanguage=VHDL
x_iplibrary=BlockDiagram x_ipname=design_1 x_ipvendor=xilinx.com x_ipversion=1.00.a
axi_bram_ctrl/1
c_bram_addr_width=13 c_bram_inst_mode=EXTERNAL c_ecc=0 c_ecc_onoff_reset_value=0
c_ecc_type=0 c_family=zynq c_fault_inject=0 c_memory_depth=8192
c_s_axi_addr_width=15 c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32 c_s_axi_data_width=32
c_s_axi_id_width=1 c_s_axi_protocol=AXI4 c_s_axi_supports_narrow_burst=0 c_select_xpm=1
c_single_port_bram=1 core_container=NA iptotal=1 x_ipcorerevision=12
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_bram_ctrl x_ipproduct=Vivado 2017.3
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=4.0
bd_afc3/1
advanced_properties=0 component_name=design_1_axi_smc_0 core_container=NA has_aresetn=1
iptotal=1 num_clks=1 num_mi=1 num_si=1
x_ipcorerevision=6 x_iplanguage=VHDL x_iplibrary=ip x_ipname=smartconnect
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
blk_mem_gen_v8_4_0/1
c_addra_width=32 c_addrb_width=32 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=8 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=128 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=1
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=1 c_est_power_summary=Estimated Power for IP _ 20.388006 mW
c_family=zynq c_has_axi_id=0 c_has_ena=1 c_has_enb=1
c_has_injecterr=0 c_has_mem_output_regs_a=1 c_has_mem_output_regs_b=1 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=1
c_has_rstb=1 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=NONE
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=131072 c_read_depth_b=131072 c_read_width_a=32 c_read_width_b=32
c_rst_priority_a=CE c_rst_priority_b=CE c_rstram_a=0 c_rstram_b=0
c_sim_collision_check=ALL c_use_bram_block=0 c_use_byte_wea=1 c_use_byte_web=1
c_use_default_data=0 c_use_ecc=0 c_use_softecc=0 c_use_uram=0
c_wea_width=4 c_web_width=4 c_write_depth_a=131072 c_write_depth_b=131072
c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=32 c_write_width_b=32
c_xdevicefamily=zynq core_container=false iptotal=1 x_ipcorerevision=0
x_iplanguage=VHDL x_iplibrary=ip x_ipname=blk_mem_gen x_ipproduct=Vivado 2017.3
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=8.4
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=0 c_ext_rst_width=4
c_family=zynq c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=12
x_iplanguage=VHDL x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2017.3
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
processing_system7_v5.5_user_configuration/1
core_container=NA iptotal=1 pcw_apu_clk_ratio_enable=6:2:1 pcw_apu_peripheral_freqmhz=666.666666
pcw_armpll_ctrl_fbdiv=30 pcw_can0_can0_io=MIO 14 .. 15 pcw_can0_grp_clk_enable=0 pcw_can0_peripheral_clksrc=External
pcw_can0_peripheral_enable=1 pcw_can0_peripheral_freqmhz=-1 pcw_can1_grp_clk_enable=0 pcw_can1_peripheral_clksrc=External
pcw_can1_peripheral_enable=0 pcw_can1_peripheral_freqmhz=-1 pcw_can_peripheral_clksrc=IO PLL pcw_can_peripheral_freqmhz=100
pcw_cpu_cpu_pll_freqmhz=1000.000 pcw_cpu_peripheral_clksrc=ARM PLL pcw_crystal_peripheral_freqmhz=33.333333 pcw_dci_peripheral_clksrc=DDR PLL
pcw_dci_peripheral_freqmhz=10.159 pcw_ddr_ddr_pll_freqmhz=1066.667 pcw_ddr_hpr_to_critical_priority_level=15 pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)
pcw_ddr_lpr_to_critical_priority_level=2 pcw_ddr_peripheral_clksrc=DDR PLL pcw_ddr_port0_hpr_enable=0 pcw_ddr_port1_hpr_enable=0
pcw_ddr_port2_hpr_enable=0 pcw_ddr_port3_hpr_enable=0 pcw_ddr_write_to_critical_priority_level=2 pcw_ddrpll_ctrl_fbdiv=32
pcw_enet0_enet0_io=MIO 16 .. 27 pcw_enet0_grp_mdio_enable=1 pcw_enet0_peripheral_clksrc=ARM PLL pcw_enet0_peripheral_enable=1
pcw_enet0_peripheral_freqmhz=1000 Mbps pcw_enet0_reset_enable=0 pcw_enet1_grp_mdio_enable=0 pcw_enet1_peripheral_clksrc=IO PLL
pcw_enet1_peripheral_enable=0 pcw_enet1_peripheral_freqmhz=1000 Mbps pcw_enet1_reset_enable=0 pcw_enet_reset_polarity=Active Low
pcw_fclk0_peripheral_clksrc=IO PLL pcw_fclk1_peripheral_clksrc=IO PLL pcw_fclk2_peripheral_clksrc=IO PLL pcw_fclk3_peripheral_clksrc=IO PLL
pcw_fpga0_peripheral_freqmhz=100 pcw_fpga1_peripheral_freqmhz=50 pcw_fpga2_peripheral_freqmhz=50 pcw_fpga3_peripheral_freqmhz=50
pcw_fpga_fclk0_enable=1 pcw_fpga_fclk1_enable=1 pcw_fpga_fclk2_enable=0 pcw_fpga_fclk3_enable=0
pcw_ftm_cti_in0=DISABLED pcw_ftm_cti_in1=DISABLED pcw_ftm_cti_in2=DISABLED pcw_ftm_cti_in3=DISABLED
pcw_ftm_cti_out0=DISABLED pcw_ftm_cti_out1=DISABLED pcw_ftm_cti_out2=DISABLED pcw_ftm_cti_out3=DISABLED
pcw_gpio_emio_gpio_enable=0 pcw_gpio_mio_gpio_enable=1 pcw_gpio_mio_gpio_io=MIO pcw_gpio_peripheral_enable=1
pcw_i2c0_grp_int_enable=1 pcw_i2c0_grp_int_io=EMIO pcw_i2c0_i2c0_io=EMIO pcw_i2c0_peripheral_enable=1
pcw_i2c0_reset_enable=0 pcw_i2c1_grp_int_enable=0 pcw_i2c1_i2c1_io=MIO 12 .. 13 pcw_i2c1_peripheral_enable=1
pcw_i2c1_reset_enable=0 pcw_i2c_reset_polarity=Active Low pcw_io_io_pll_freqmhz=1600.000 pcw_iopll_ctrl_fbdiv=48
pcw_irq_f2p_mode=DIRECT pcw_m_axi_gp0_freqmhz=100 pcw_m_axi_gp1_freqmhz=10 pcw_nand_cycles_t_ar=1
pcw_nand_cycles_t_clr=1 pcw_nand_cycles_t_rc=11 pcw_nand_cycles_t_rea=1 pcw_nand_cycles_t_rr=1
pcw_nand_cycles_t_wc=11 pcw_nand_cycles_t_wp=1 pcw_nand_grp_d8_enable=0 pcw_nand_peripheral_enable=0
pcw_nor_cs0_t_ceoe=1 pcw_nor_cs0_t_pc=1 pcw_nor_cs0_t_rc=11 pcw_nor_cs0_t_tr=1
pcw_nor_cs0_t_wc=11 pcw_nor_cs0_t_wp=1 pcw_nor_cs0_we_time=0 pcw_nor_cs1_t_ceoe=1
pcw_nor_cs1_t_pc=1 pcw_nor_cs1_t_rc=11 pcw_nor_cs1_t_tr=1 pcw_nor_cs1_t_wc=11
pcw_nor_cs1_t_wp=1 pcw_nor_cs1_we_time=0 pcw_nor_grp_a25_enable=0 pcw_nor_grp_cs0_enable=0
pcw_nor_grp_cs1_enable=0 pcw_nor_grp_sram_cs0_enable=0 pcw_nor_grp_sram_cs1_enable=0 pcw_nor_grp_sram_int_enable=0
pcw_nor_peripheral_enable=0 pcw_nor_sram_cs0_t_ceoe=1 pcw_nor_sram_cs0_t_pc=1 pcw_nor_sram_cs0_t_rc=11
pcw_nor_sram_cs0_t_tr=1 pcw_nor_sram_cs0_t_wc=11 pcw_nor_sram_cs0_t_wp=1 pcw_nor_sram_cs0_we_time=0
pcw_nor_sram_cs1_t_ceoe=1 pcw_nor_sram_cs1_t_pc=1 pcw_nor_sram_cs1_t_rc=11 pcw_nor_sram_cs1_t_tr=1
pcw_nor_sram_cs1_t_wc=11 pcw_nor_sram_cs1_t_wp=1 pcw_nor_sram_cs1_we_time=0 pcw_override_basic_clock=0
pcw_pcap_peripheral_clksrc=IO PLL pcw_pcap_peripheral_freqmhz=200 pcw_pjtag_peripheral_enable=0 pcw_preset_bank0_voltage=LVCMOS 3.3V
pcw_preset_bank1_voltage=LVCMOS 1.8V pcw_qspi_grp_fbclk_enable=1 pcw_qspi_grp_fbclk_io=MIO 8 pcw_qspi_grp_io1_enable=0
pcw_qspi_grp_single_ss_enable=1 pcw_qspi_grp_single_ss_io=MIO 1 .. 6 pcw_qspi_grp_ss1_enable=0 pcw_qspi_internal_highaddress=0xFCFFFFFF
pcw_qspi_peripheral_clksrc=IO PLL pcw_qspi_peripheral_enable=1 pcw_qspi_peripheral_freqmhz=200.000000 pcw_qspi_qspi_io=MIO 1 .. 6
pcw_s_axi_acp_freqmhz=10 pcw_s_axi_gp0_freqmhz=10 pcw_s_axi_gp1_freqmhz=10 pcw_s_axi_hp0_data_width=64
pcw_s_axi_hp0_freqmhz=100 pcw_s_axi_hp1_data_width=64 pcw_s_axi_hp1_freqmhz=10 pcw_s_axi_hp2_data_width=64
pcw_s_axi_hp2_freqmhz=10 pcw_s_axi_hp3_data_width=64 pcw_s_axi_hp3_freqmhz=10 pcw_sd0_grp_cd_enable=1
pcw_sd0_grp_cd_io=MIO 46 pcw_sd0_grp_pow_enable=0 pcw_sd0_grp_wp_enable=1 pcw_sd0_grp_wp_io=MIO 47
pcw_sd0_peripheral_enable=1 pcw_sd0_sd0_io=MIO 40 .. 45 pcw_sd1_grp_cd_enable=0 pcw_sd1_grp_pow_enable=0
pcw_sd1_grp_wp_enable=0 pcw_sd1_peripheral_enable=0 pcw_sdio_peripheral_clksrc=IO PLL pcw_sdio_peripheral_freqmhz=100
pcw_single_qspi_data_mode=x4 pcw_smc_peripheral_clksrc=IO PLL pcw_smc_peripheral_freqmhz=100 pcw_spi0_grp_ss0_enable=0
pcw_spi0_grp_ss1_enable=0 pcw_spi0_grp_ss2_enable=0 pcw_spi0_peripheral_enable=0 pcw_spi1_grp_ss0_enable=0
pcw_spi1_grp_ss1_enable=0 pcw_spi1_grp_ss2_enable=0 pcw_spi1_peripheral_enable=0 pcw_spi_peripheral_clksrc=IO PLL
pcw_spi_peripheral_freqmhz=166.666666 pcw_tpiu_peripheral_clksrc=External pcw_tpiu_peripheral_freqmhz=200 pcw_trace_grp_16bit_enable=0
pcw_trace_grp_2bit_enable=0 pcw_trace_grp_32bit_enable=0 pcw_trace_grp_4bit_enable=0 pcw_trace_grp_8bit_enable=0
pcw_trace_peripheral_enable=0 pcw_ttc0_clk0_peripheral_clksrc=CPU_1X pcw_ttc0_clk0_peripheral_freqmhz=133.333333 pcw_ttc0_clk1_peripheral_clksrc=CPU_1X
pcw_ttc0_clk1_peripheral_freqmhz=133.333333 pcw_ttc0_clk2_peripheral_clksrc=CPU_1X pcw_ttc0_clk2_peripheral_freqmhz=133.333333 pcw_ttc0_peripheral_enable=1
pcw_ttc0_ttc0_io=EMIO pcw_ttc1_clk0_peripheral_clksrc=CPU_1X pcw_ttc1_clk0_peripheral_freqmhz=133.333333 pcw_ttc1_clk1_peripheral_clksrc=CPU_1X
pcw_ttc1_clk1_peripheral_freqmhz=133.333333 pcw_ttc1_clk2_peripheral_clksrc=CPU_1X pcw_ttc1_clk2_peripheral_freqmhz=133.333333 pcw_ttc1_peripheral_enable=0
pcw_ttc_peripheral_freqmhz=50 pcw_uart0_baud_rate=115200 pcw_uart0_grp_full_enable=0 pcw_uart0_peripheral_enable=1
pcw_uart0_uart0_io=MIO 10 .. 11 pcw_uart1_baud_rate=115200 pcw_uart1_grp_full_enable=0 pcw_uart1_peripheral_enable=1
pcw_uart1_uart1_io=MIO 48 .. 49 pcw_uart_peripheral_clksrc=IO PLL pcw_uart_peripheral_freqmhz=100 pcw_uiparam_ddr_adv_enable=0
pcw_uiparam_ddr_al=0 pcw_uiparam_ddr_bank_addr_count=3 pcw_uiparam_ddr_bl=8 pcw_uiparam_ddr_board_delay0=0.271
pcw_uiparam_ddr_board_delay1=0.259 pcw_uiparam_ddr_board_delay2=0.219 pcw_uiparam_ddr_board_delay3=0.207 pcw_uiparam_ddr_bus_width=32 Bit
pcw_uiparam_ddr_cl=7 pcw_uiparam_ddr_clock_0_length_mm=0 pcw_uiparam_ddr_clock_0_package_length=80.4535 pcw_uiparam_ddr_clock_0_propogation_delay=160
pcw_uiparam_ddr_clock_1_length_mm=0 pcw_uiparam_ddr_clock_1_package_length=80.4535 pcw_uiparam_ddr_clock_1_propogation_delay=160 pcw_uiparam_ddr_clock_2_length_mm=0
pcw_uiparam_ddr_clock_2_package_length=80.4535 pcw_uiparam_ddr_clock_2_propogation_delay=160 pcw_uiparam_ddr_clock_3_length_mm=0 pcw_uiparam_ddr_clock_3_package_length=80.4535
pcw_uiparam_ddr_clock_3_propogation_delay=160 pcw_uiparam_ddr_clock_stop_en=0 pcw_uiparam_ddr_col_addr_count=10 pcw_uiparam_ddr_cwl=6
pcw_uiparam_ddr_device_capacity=4096 MBits pcw_uiparam_ddr_dq_0_length_mm=0 pcw_uiparam_ddr_dq_0_package_length=98.503 pcw_uiparam_ddr_dq_0_propogation_delay=160
pcw_uiparam_ddr_dq_1_length_mm=0 pcw_uiparam_ddr_dq_1_package_length=68.5855 pcw_uiparam_ddr_dq_1_propogation_delay=160 pcw_uiparam_ddr_dq_2_length_mm=0
pcw_uiparam_ddr_dq_2_package_length=90.295 pcw_uiparam_ddr_dq_2_propogation_delay=160 pcw_uiparam_ddr_dq_3_length_mm=0 pcw_uiparam_ddr_dq_3_package_length=103.977
pcw_uiparam_ddr_dq_3_propogation_delay=160 pcw_uiparam_ddr_dqs_0_length_mm=0 pcw_uiparam_ddr_dqs_0_package_length=105.056 pcw_uiparam_ddr_dqs_0_propogation_delay=160
pcw_uiparam_ddr_dqs_1_length_mm=0 pcw_uiparam_ddr_dqs_1_package_length=66.904 pcw_uiparam_ddr_dqs_1_propogation_delay=160 pcw_uiparam_ddr_dqs_2_length_mm=0
pcw_uiparam_ddr_dqs_2_package_length=89.1715 pcw_uiparam_ddr_dqs_2_propogation_delay=160 pcw_uiparam_ddr_dqs_3_length_mm=0 pcw_uiparam_ddr_dqs_3_package_length=113.63
pcw_uiparam_ddr_dqs_3_propogation_delay=160 pcw_uiparam_ddr_dqs_to_clk_delay_0=0.229 pcw_uiparam_ddr_dqs_to_clk_delay_1=0.250 pcw_uiparam_ddr_dqs_to_clk_delay_2=0.121
pcw_uiparam_ddr_dqs_to_clk_delay_3=0.146 pcw_uiparam_ddr_dram_width=16 Bits pcw_uiparam_ddr_ecc=Disabled pcw_uiparam_ddr_enable=1
pcw_uiparam_ddr_freq_mhz=533.333333 pcw_uiparam_ddr_high_temp=Normal (0-85) pcw_uiparam_ddr_memory_type=DDR 3 pcw_uiparam_ddr_partno=MT41J256M16 RE-125
pcw_uiparam_ddr_row_addr_count=15 pcw_uiparam_ddr_speed_bin=DDR3_1066F pcw_uiparam_ddr_t_faw=40.0 pcw_uiparam_ddr_t_ras_min=35.0
pcw_uiparam_ddr_t_rc=48.91 pcw_uiparam_ddr_t_rcd=7 pcw_uiparam_ddr_t_rp=7 pcw_uiparam_ddr_train_data_eye=1
pcw_uiparam_ddr_train_read_gate=1 pcw_uiparam_ddr_train_write_level=1 pcw_uiparam_ddr_use_internal_vref=0 pcw_usb0_peripheral_enable=1
pcw_usb0_peripheral_freqmhz=60 pcw_usb0_reset_enable=1 pcw_usb0_reset_io=MIO 51 pcw_usb0_usb0_io=MIO 28 .. 39
pcw_usb1_peripheral_enable=0 pcw_usb1_peripheral_freqmhz=60 pcw_usb1_reset_enable=0 pcw_usb_reset_polarity=Active Low
pcw_use_cross_trigger=0 pcw_use_m_axi_gp0=1 pcw_use_m_axi_gp1=0 pcw_use_s_axi_acp=0
pcw_use_s_axi_gp0=0 pcw_use_s_axi_gp1=0 pcw_use_s_axi_hp0=1 pcw_use_s_axi_hp1=0
pcw_use_s_axi_hp2=0 pcw_use_s_axi_hp3=0 pcw_wdt_peripheral_clksrc=CPU_1X pcw_wdt_peripheral_enable=0
pcw_wdt_peripheral_freqmhz=133.333333
processing_system7_v5_5_processing_system7/1
c_dm_width=4 c_dq_width=32 c_dqs_width=4 c_emio_gpio_width=64
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_pjtag=0 c_en_emio_trace=0
c_fclk_clk0_buf=TRUE c_fclk_clk1_buf=TRUE c_fclk_clk2_buf=FALSE c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 c_gp1_en_modifiable_txn=1 c_include_acp_trans_check=0 c_include_trace_buffer=0
c_irq_f2p_mode=DIRECT c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp0_id_width=12 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_thread_id_width=12 c_mio_primitive=54
c_num_f2p_intr_inputs=1 c_package_name=clg400 c_ps7_si_rev=PRODUCTION c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 c_s_axi_acp_id_width=3 c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp0_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp2_id_width=6 c_s_axi_hp3_data_width=64 c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 c_trace_buffer_fifo_size=128 c_trace_internal_width=2 c_trace_pipeline_width=8
c_use_axi_nonsecure=0 c_use_default_acp_user_val=0 c_use_m_axi_gp0=1 c_use_m_axi_gp1=0
c_use_s_axi_acp=0 c_use_s_axi_gp0=0 c_use_s_axi_gp1=0 c_use_s_axi_hp0=1
c_use_s_axi_hp1=0 c_use_s_axi_hp2=0 c_use_s_axi_hp3=0 core_container=NA
iptotal=1 use_trace_data_edge_detector=0 x_ipcorerevision=6 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=processing_system7 x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=5.5
sc_exit_v1_0_5_top/1
c_addr_width=15 c_enable_pipelining=0x1 c_family=zynq c_has_lock=0
c_is_cascaded=0 c_m_aruser_width=0 c_m_awuser_width=0 c_m_buser_width=0
c_m_id_width=0 c_m_limit_read_length=16 c_m_limit_write_length=16 c_m_protocol=0
c_m_ruser_bits_per_byte=0 c_m_ruser_width=0 c_m_wuser_bits_per_byte=0 c_m_wuser_width=0
c_max_ruser_bits_per_byte=0 c_max_wuser_bits_per_byte=0 c_mep_identifier_width=1 c_num_msc=1
c_rdata_width=32 c_read_acceptance=1 c_s_id_width=1 c_single_issuing=0
c_ssc_route_array=0b01 c_ssc_route_width=1 c_wdata_width=32 c_write_acceptance=1
core_container=NA iptotal=1 x_ipcorerevision=5 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=sc_exit x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
sc_mmu_v1_0_5_top/1
c_addr_width=32 c_enable_pipelining=0x1 c_family=zynq c_id_width=12
c_is_cascaded=0 c_msc_route_array=0b1 c_msc_route_width=1 c_num_msc=1
c_num_seg=1 c_rdata_width=32 c_read_acceptance=32 c_s_aruser_width=0
c_s_awuser_width=0 c_s_buser_width=0 c_s_protocol=1 c_s_ruser_width=0
c_s_wuser_width=0 c_seg_base_addr_array=0x0000000040000000 c_seg_secure_read_array=0b0 c_seg_secure_write_array=0b0
c_seg_sep_route_array=0x0000000000000000 c_seg_size_array=0x0000000f c_seg_supports_read_array=0x1 c_seg_supports_write_array=0x1
c_single_issuing=0 c_supports_read_decerr=1 c_supports_wrap=1 c_supports_write_decerr=1
c_wdata_width=32 c_write_acceptance=32 core_container=NA iptotal=1
x_ipcorerevision=5 x_iplanguage=VHDL x_iplibrary=ip x_ipname=sc_mmu
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_node_v1_0_6_top/1
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=2 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_size=5 c_fifo_type=0 c_id_width=1
c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0 c_max_payld_bytes=4
c_num_mi=1 c_num_si=1 c_payld_width=138 c_s_latency=0
c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1 c_synchronization_stages=3
c_user_bits_per_byte=0 c_user_width=0 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VHDL x_iplibrary=ip x_ipname=sc_node
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_node_v1_0_6_top/2
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=3 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_size=5 c_fifo_type=0 c_id_width=1
c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0 c_max_payld_bytes=4
c_num_mi=1 c_num_si=1 c_payld_width=138 c_s_latency=0
c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1 c_synchronization_stages=3
c_user_bits_per_byte=0 c_user_width=0 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VHDL x_iplibrary=ip x_ipname=sc_node
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_node_v1_0_6_top/3
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=4 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_size=5 c_fifo_type=0 c_id_width=1
c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0 c_max_payld_bytes=4
c_num_mi=1 c_num_si=1 c_payld_width=5 c_s_latency=0
c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1 c_synchronization_stages=3
c_user_bits_per_byte=0 c_user_width=0 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VHDL x_iplibrary=ip x_ipname=sc_node
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_node_v1_0_6_top/4
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=0 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_size=5 c_fifo_type=0 c_id_width=1
c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0 c_max_payld_bytes=4
c_num_mi=1 c_num_si=1 c_payld_width=51 c_s_latency=0
c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1 c_synchronization_stages=3
c_user_bits_per_byte=0 c_user_width=512 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VHDL x_iplibrary=ip x_ipname=sc_node
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_node_v1_0_6_top/5
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=1 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_size=5 c_fifo_type=0 c_id_width=1
c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0 c_max_payld_bytes=4
c_num_mi=1 c_num_si=1 c_payld_width=52 c_s_latency=0
c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1 c_synchronization_stages=3
c_user_bits_per_byte=0 c_user_width=512 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VHDL x_iplibrary=ip x_ipname=sc_node
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_si_converter_v1_0_5_top/1
c_addr_width=32 c_enable_pipelining=0x1 c_has_burst=1 c_id_width=1
c_is_cascaded=0 c_limit_read_length=0 c_limit_write_length=0 c_max_ruser_bits_per_byte=0
c_max_wuser_bits_per_byte=0 c_mep_identifier_width=1 c_msc_rdata_width_array=0x00000020 c_msc_wdata_width_array=0x00000020
c_num_msc=1 c_num_read_threads=1 c_num_seg=1 c_num_write_threads=1
c_rdata_width=32 c_read_acceptance=32 c_read_watermark=0 c_s_ruser_bits_per_byte=0
c_s_wuser_bits_per_byte=0 c_sep_protocol_array=0x00000000 c_sep_rdata_width_array=0x00000020 c_sep_wdata_width_array=0x00000020
c_single_issuing=0 c_supports_narrow=0 c_wdata_width=32 c_write_acceptance=32
c_write_watermark=0 core_container=NA iptotal=1 x_ipcorerevision=5
x_iplanguage=VHDL x_iplibrary=ip x_ipname=sc_si_converter x_ipproduct=Vivado 2017.3
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_transaction_regulator_v1_0_6_top/1
c_addr_width=32 c_enable_pipelining=0x1 c_family=zynq c_is_cascaded=0
c_m_id_width=1 c_mep_identifier=0 c_mep_identifier_width=1 c_num_read_threads=1
c_num_write_threads=1 c_rdata_width=32 c_read_acceptance=32 c_s_id_width=12
c_sep_route_width=1 c_single_issuing=0 c_supports_read_deadlock=0 c_supports_write_deadlock=0
c_wdata_width=32 c_write_acceptance=32 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VHDL x_iplibrary=ip x_ipname=sc_transaction_regulator
x_ipproduct=Vivado 2017.3 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
xpm_memory_base/1
x_ipversion=1.0 addr_width_a=5 addr_width_b=5 auto_sleep_time=0
byte_write_width_a=70 byte_write_width_b=70 clocking_mode=0 core_container=NA
ecc_mode=0 iptotal=5 max_num_char=0 memory_optimization=true
memory_primitive=1 memory_size=2240 memory_type=1 message_control=0
num_char_loc=0 p_ecc_mode=no_ecc p_enable_byte_write_a=0 p_enable_byte_write_b=0
p_max_depth_data=32 p_memory_opt=yes p_memory_primitive=distributed p_min_width_data=70
p_min_width_data_a=70 p_min_width_data_b=70 p_min_width_data_ecc=70 p_min_width_data_ldw=4
p_min_width_data_shft=70 p_num_cols_write_a=1 p_num_cols_write_b=1 p_num_rows_read_a=1
p_num_rows_read_b=1 p_num_rows_write_a=1 p_num_rows_write_b=1 p_sdp_write_mode=yes
p_width_addr_lsb_read_a=0 p_width_addr_lsb_read_b=0 p_width_addr_lsb_write_a=0 p_width_addr_lsb_write_b=0
p_width_addr_read_a=5 p_width_addr_read_b=5 p_width_addr_write_a=5 p_width_addr_write_b=5
p_width_col_write_a=70 p_width_col_write_b=70 read_data_width_a=70 read_data_width_b=70
read_latency_a=2 read_latency_b=0 read_reset_value_a=0 read_reset_value_b=0
use_embedded_constraint=0 use_mem_init=0 version=0 wakeup_time=0
write_data_width_a=70 write_data_width_b=70 write_mode_a=0 write_mode_b=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
pdrc-153=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-17=112 timing-18=3 timing-20=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") bram=0.005748 clocks=0.011087
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.145640 die=xc7z020clg400-1 dsp_output_toggle=12.500000 dynamic=1.526617
effective_thetaja=11.5 enable_probability=0.990000 family=zynq ff_toggle=12.500000
flow_state=routed heatsink=none i/o=0.000318 input_toggle=12.500000
junction_temp=44.3 (C) logic=0.006068 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000 mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=1.672257 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=clg400 pct_clock_constrained=4.000000 pct_inputs_defined=0 platform=nt64
process=typical ps7=1.495524 ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.007872
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=7.4 (C/W) thetasa=0.0 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=11.5 user_junc_temp=44.3 (C) user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.000011 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.015107 vccaux_total_current=0.015118 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000479 vccbram_static_current=0.001903 vccbram_total_current=0.002382 vccbram_voltage=1.000000
vccint_dynamic_current=0.030303 vccint_static_current=0.015243 vccint_total_current=0.045546 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000088 vcco33_static_current=0.001000 vcco33_total_current=0.001088 vcco33_voltage=3.300000
vcco_ddr_dynamic_current=0.456904 vcco_ddr_static_current=0.002000 vcco_ddr_total_current=0.458904 vcco_ddr_voltage=1.500000
vcco_mio0_dynamic_current=0.001750 vcco_mio0_static_current=0.001000 vcco_mio0_total_current=0.002750 vcco_mio0_voltage=3.300000
vcco_mio1_dynamic_current=0.002187 vcco_mio1_static_current=0.001000 vcco_mio1_total_current=0.003187 vcco_mio1_voltage=1.800000
vccpaux_dynamic_current=0.051341 vccpaux_static_current=0.010330 vccpaux_total_current=0.061671 vccpaux_voltage=1.800000
vccpint_dynamic_current=0.681828 vccpint_static_current=0.029908 vccpint_total_current=0.711736 vccpint_voltage=1.000000
vccpll_dynamic_current=0.014563 vccpll_static_current=0.003000 vccpll_total_current=0.017563 vccpll_voltage=1.800000
version=2017.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=1 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=1 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=16 block_ram_tile_util_percentage=11.43
ramb18_available=280 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=16 ramb36_fifo_util_percentage=11.43
ramb36e1_only_used=16
primitives
bibuf_functional_category=IO bibuf_used=130 bufg_functional_category=Clock bufg_used=1
carry4_functional_category=CarryLogic carry4_used=20 fdce_functional_category=Flop & Latch fdce_used=32
fdpe_functional_category=Flop & Latch fdpe_used=1 fdre_functional_category=Flop & Latch fdre_used=1895
fdse_functional_category=Flop & Latch fdse_used=108 ibuf_functional_category=IO ibuf_used=2
ldce_functional_category=Flop & Latch ldce_used=1 lut1_functional_category=LUT lut1_used=42
lut2_functional_category=LUT lut2_used=215 lut3_functional_category=LUT lut3_used=254
lut4_functional_category=LUT lut4_used=666 lut5_functional_category=LUT lut5_used=246
lut6_functional_category=LUT lut6_used=566 muxf7_functional_category=MuxFx muxf7_used=34
obuf_functional_category=IO obuf_used=3 ps7_functional_category=Specialized Resource ps7_used=1
ramb36e1_functional_category=Block Memory ramb36e1_used=16 ramd32_functional_category=Distributed Memory ramd32_used=162
rams32_functional_category=Distributed Memory rams32_used=54 srl16e_functional_category=Distributed Memory srl16e_used=34
srlc32e_functional_category=Distributed Memory srlc32e_used=132
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=34 f7_muxes_util_percentage=0.13
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=108 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=1765 lut_as_logic_util_percentage=3.32 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=274 lut_as_memory_util_percentage=1.57 lut_as_shift_register_fixed=0 lut_as_shift_register_used=166
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=2036 register_as_flip_flop_util_percentage=1.91
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=1 register_as_latch_util_percentage=<0.01
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=2039 slice_luts_util_percentage=3.83
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=2037 slice_registers_util_percentage=1.91
fully_used_lut_ff_pairs_fixed=1.91 fully_used_lut_ff_pairs_used=85 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=108
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=1765 lut_as_logic_util_percentage=3.32
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=274 lut_as_memory_util_percentage=1.57
lut_as_shift_register_fixed=0 lut_as_shift_register_used=166 lut_ff_pairs_with_one_unused_flip_flop_fixed=166 lut_ff_pairs_with_one_unused_flip_flop_used=1011
lut_ff_pairs_with_one_unused_lut_output_fixed=1011 lut_ff_pairs_with_one_unused_lut_output_used=1054 lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=1175 lut_flip_flop_pairs_util_percentage=2.21 slice_available=13300 slice_fixed=0
slice_used=745 slice_util_percentage=5.60 slicel_fixed=0 slicel_used=474
slicem_fixed=0 slicem_used=271 unique_control_sets_used=117 using_o5_and_o6_fixed=117
using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=32 using_o6_output_only_fixed=32
using_o6_output_only_used=134
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=2296692 bogomips=0 bram18=0 bram36=16
bufg=0 bufr=0 congestion_level=0 ctrls=117
dsp=0 effort=2 estimated_expansions=2915364 ff=2037
global_clocks=1 high_fanout_nets=2 iob=5 lut=2176
movable_instances=4849 nets=6411 pins=32919 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z020clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:34s hls_ip=0 memory_gain=435.441MB memory_peak=732.355MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::