library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity crc_tb is
--  Port ( );
end crc_tb;

architecture Behavioral of crc_tb is
 signal clk_tb : std_logic;
 signal data_tb  : std_logic_vector(7 downto 0);
 signal LOAD_INIT_tb: std_logic:='1';
 signal calc_tb: std_logic:='0';
 signal d_valid_tb: std_logic := '0';
 signal reset_tb : std_logic;
 signal byte_crc_cnt : unsigned (15 downto 0):= X"0000";
 signal enable_test : std_logic:= '0';
signal              CRC_REG_tb             :    std_logic_vector(31 downto 0);

 --
 component CRC is
 Port (  CLOCK               :   in  std_logic;
            RESET               :   in  std_logic;
            DATA                :   in  std_logic_vector(7 downto 0);
            LOAD_INIT           :   in  std_logic;
            CALC                :   in  std_logic;
            D_VALID             :   in  std_logic;
            CRC                 :   out std_logic_vector(7 downto 0);
            CRC_REG             :   out std_logic_vector(31 downto 0);
            CRC_VALID           :   out std_logic
         );
end component;


begin
--
clk_p : process 
begin
    clk_tb <= '1';
    wait for 10 ns;
    clk_tb <= '0';
    wait for 10 ns;
end process;

---
reset_p : process 
begin 
  
    LOAD_INIT_tb <= '1';
    reset_tb <= '1';
    wait for 100 ns;
    reset_tb <= '0';
    wait for 100 ns;
    LOAD_INIT_tb <= '0';
    while  CRC_REG_tb < X"FFFFFFFF" loop
    wait for 10 ns;
    end loop; 
    
  wait for 100 ns;       
        enable_test <= '1';
    wait;
end process;
--
CRC_tb : CRC 

port map(
    CLOCK => clk_tb,
    RESET => reset_tb,
    DATA => data_tb,
    LOAD_INIt => LOAD_INIT_tb,
    CALC => calc_tb,
    D_VALID =>d_valid_tb,
    CRC => open,
    CRC_REG => CRC_REG_tb,
    CRC_VALID => open
);


crc_test : process ( clk_tb, reset_tb,byte_crc_cnt,d_valid_tb,enable_test) 
begin

  if ( enable_test = '1') then  
    if (rising_edge(clk_tb) and reset_tb = '0' and to_integer(byte_crc_cnt) < 4) then
       -- 
        d_valid_tb <= '1';
        calc_tb <= '1';
        data_tb <= X"FF";
        byte_crc_cnt <= byte_crc_cnt +1;
    else
   
    if to_integer(byte_crc_cnt) >= 4 then
    d_valid_tb <= '0';
            calc_tb <= '0';

    else
    end if;
    
    
    
    end if;
    
    else
    
    --d_valid_tb <= '1';
    end if;

end process;


end Behavioral;