LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY ULoop IS
    PORT (
        -- System clock. (10 MHz)
        clk : IN STD_LOGIC;

        -- Reset.
        rst : IN STD_LOGIC;

        -- Incoming serial stream.
        rx : IN STD_LOGIC;

        -- Outgoing serial stream.
        tx : OUT STD_LOGIC

        -- Debug output (input/output bytes)
        --led_input : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        --led_output : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END ULoop;

ARCHITECTURE ULoop_arch OF ULoop IS
    COMPONENT uart
        GENERIC (
            clk_cycles_per_bit : INTEGER
        );
        PORT (
            clk : IN STD_LOGIC;
            rst : IN STD_LOGIC;

            rx_port : IN STD_LOGIC;
            rx_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
            rx_ack : IN STD_LOGIC;
            rx_rdy : OUT STD_LOGIC := '0';

            tx_port : OUT STD_LOGIC := '1';
            tx_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            tx_ack : IN STD_LOGIC;
            tx_rdy : OUT STD_LOGIC := '1'
        );
    END COMPONENT;

    -- Receiver signals.
    SIGNAL s_rx_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL s_rx_ack : STD_LOGIC;
    SIGNAL s_rx_rdy : STD_LOGIC;

    -- Transmitter signals.
    SIGNAL s_tx_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL s_tx_ack : STD_LOGIC;
    SIGNAL s_tx_rdy : STD_LOGIC;

    -- fsm
    TYPE states IS (s_Idle, s_Read, s_Write, s_Send);
    SIGNAL state : states := s_Idle;

    -- Intern signals
    SIGNAL s_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0); -- input buffer
    SIGNAL s_output : STD_LOGIC_VECTOR(7 DOWNTO 0); -- output buffer
BEGIN
    --    -- Debug Output
    --    led_input <= s_buffer;   
    --    led_output <= s_output;

    -- Uart instance (contains Rx and Tx)
    uartp : uart
    GENERIC MAP(
        clk_cycles_per_bit => 87 -- 10 MHz / 115_200 baudrate = 87
    )
    PORT MAP(
        clk => clk, -- System clock. (10 MHz)
        rst => rst, -- Reset
        rx_port => rx, -- serial rx stream
        rx_data => s_rx_data, -- input byte
        rx_ack => s_rx_ack, -- recv handshake
        rx_rdy => s_rx_rdy, -- shows if recv is ready
        tx_port => tx, -- recv has received new byte
        tx_data => s_tx_data, -- byte to send
        tx_ack => s_tx_ack, -- transmitter handshake
        tx_rdy => s_tx_rdy -- transmitter is ready to accept new byte
    );

    fsm : PROCESS (clk)
    BEGIN
        IF rising_edge(clk) THEN
            IF rst = '1' THEN
                -- Synchronous reset.
                state <= s_Idle;
                s_rx_ack <= '0';
                s_tx_ack <= '0';
                s_output <= (OTHERS => '0');
                s_buffer <= (OTHERS => '0');
            ELSE
                CASE state IS
                    WHEN s_Idle =>
                        IF s_rx_rdy = '1' THEN
                            s_buffer <= s_rx_data; -- 
                            s_rx_ack <= '1';
                            state <= s_Read;
                        ELSE
                            s_rx_ack <= '0';
                            s_tx_ack <= '0';
                            --s_output <= (others => '0');
                            --s_buffer <= (others => '0');
                        END IF;

                    WHEN s_Read =>
                        s_rx_ack <= '0';

                        -- Debug! (Lothar M.)
                        s_output <= x"55";
                        state <= s_Write;
                        -- End Debug!

                        -- Vereinfachte Dekodierung in Kommando/Datenbyte (funktioniert nicht)                  
--                      if s_buffer(0) = '1' then
--                          -- cmd
--                          if s_buffer(1) = '1' then
--                              --s_output <= "00001111";
--                              state <= s_Write;
--                          elsif s_buffer(1) = '0' then
--                              --s_output <= "11110000";
--                              state <= s_Write;
--                          end if;                                
--                      else
--                          -- data
--                          --s_output <= "11001100";--s_buffer;
--                          state <= s_Write;
--                      end if;                     

                    WHEN s_Write =>
                        IF s_tx_rdy = '1' THEN
                            s_tx_data <= s_output;
                            s_tx_ack <= '1';
                            state <= s_Send;
                        END IF;

                    WHEN s_Send =>
                        s_tx_ack <= '0';
                        state <= s_Idle;

                END CASE;
            END IF;
        END IF;
    END PROCESS fsm;
END ULoop_arch;