.syntax unified .cpu cortex-m4 .thumb @ GPIO register map is similiar to STM32F4 chips. @ -> register boundary address pp. 65 in DM00031020.pdf .equ BIT0, 0x00000001 .equ BIT1, 0x00000002 .equ BIT2, 0x00000004 .equ BIT3, 0x00000008 .equ BIT4, 0x00000010 .equ BIT5, 0x00000020 .equ BIT6, 0x00000040 .equ BIT7, 0x00000080 .equ BIT8, 0x00000100 .equ BIT9, 0x00000200 .equ BIT10, 0x00000400 .equ BIT11, 0x00000800 .equ BIT12, 0x00001000 .equ BIT13, 0x00002000 .equ BIT14, 0x00004000 .equ BIT15, 0x00008000 .equ BIT16, 0x00010000 .equ BIT17, 0x00020000 .equ BIT18, 0x00040000 .equ BIT19, 0x00080000 .equ BIT20, 0x00100000 .equ BIT21, 0x00200000 .equ BIT22, 0x00400000 .equ BIT23, 0x00800000 .equ BIT24, 0x01000000 .equ BIT25, 0x02000000 .equ BIT26, 0x04000000 .equ BIT27, 0x08000000 .equ BIT28, 0x10000000 .equ BIT29, 0x20000000 .equ BIT30, 0x40000000 .equ BIT31, 0x80000000 .equ GPIOE_BASE , 0x40021000 .equ GPIOE_MODER , GPIOE_BASE + 0x00 @ pp. 287 of DM00031020.pdf .equ GPIOE_OTYPER , GPIOE_BASE + 0x04 .equ GPIOE_ODR , GPIOE_BASE + 0x14 .equ GPIOB_BASE , 0x40020400 .equ GPIOB_MODER , GPIOB_BASE + 0x00 .equ GPIOB_OTYPER , GPIOB_BASE + 0x04 .equ GPIOB_OSPEEDR , GPIOB_BASE + 0x08 .equ GPIOB_PUPDR , GPIOB_BASE + 0x0C .equ GPIOB_IDR , GPIOB_BASE + 0x10 .equ GPIOB_ODR , GPIOB_BASE + 0x14 .equ GPIOB_BSRR , GPIOB_BASE + 0x18 .equ GPIOB_LCKR , GPIOB_BASE + 0x1C .equ GPIOB_AFRL , GPIOB_BASE + 0x20 .equ GPIOB_AFRH , GPIOB_BASE + 0x24 .equ GPIOB_BRR , GPIOB_BASE + 0x28 @ System control registers .equ RCC_BASE , 0x40023800 .equ RCC_CR , RCC_BASE + 0x00 .equ RCC_CFGR , RCC_BASE + 0x08 .equ RCC_AHB1ENR , RCC_BASE + 0x30 .equ RCC_AHB2ENR , RCC_BASE + 0x34 .equ RCC_APB1ENR , RCC_BASE + 0x40 .equ RCC_APB2ENR , RCC_BASE + 0x44 @ USART3 on STM32F4 chips: @ USART3 on STM32F1/STM32F4 chips: pp. 1018 in RM0090 (dm00031020-stm*.pdf) .equ USART3_BASE , 0x40004800 .equ USART3_SR , USART3_BASE + 0x00 .equ USART3_DR , USART3_BASE + 0x04 .equ USART3_BRR , USART3_BASE + 0x08 .equ USART3_CR1 , USART3_BASE + 0x0C .equ USART3_CR2 , USART3_BASE + 0x10 .equ USART3_CR3 , USART3_BASE + 0x14 .equ USART3_GPTR , USART3_BASE + 0x18 @ Flags for USART3_ISR register: .equ RXNE , BIT5 .equ TC , BIT6 .equ TXE , BIT7 .equ HSERDY , BIT17 .equ HSEON , BIT16 @ GPIO register map is similiar to STM32F4 chips. @ -> register boundary address pp. 65 in DM00031020.pdf .equ GPIOE_BASE , 0x40021000 .equ GPIOE_MODER , GPIOE_BASE + 0x00 @ pp. 287 of DM00031020.pdf .equ GPIOE_OTYPER , GPIOE_BASE + 0x04 .equ GPIOE_ODR , GPIOE_BASE + 0x14 .equ GPIOB_BASE, 0x40020400 .equ GPIOB_MODER , GPIOB_BASE + 0x00 @<<<<< .equ GPIOB_AFRL , GPIOB_BASE + 0x20 @<<<<< .equ GPIOB_AFRH , GPIOB_BASE + 0x24 .equ GPIOA_BASE , 0x40020000 .equ GPIOA_MODER , GPIOA_BASE + 0x00 .equ GPIOA_OTYPER , GPIOA_BASE + 0x04 .equ GPIOA_OSPEEDR , GPIOA_BASE + 0x08 .equ GPIOA_PUPDR , GPIOA_BASE + 0x0C .equ GPIOA_IDR , GPIOA_BASE + 0x10 .equ GPIOA_ODR , GPIOA_BASE + 0x14 .equ GPIOA_BSRR , GPIOA_BASE + 0x18 .equ GPIOA_LCKR , GPIOA_BASE + 0x1C .equ GPIOA_AFRL , GPIOA_BASE + 0x20 .equ GPIOA_AFRH , GPIOA_BASE + 0x24 .equ RCC_BASE , 0x40023800 .equ RCC_CR , RCC_BASE + 0x00 .equ RCC_CFGR , RCC_BASE + 0x08 .equ RCC_AHB1ENR , RCC_BASE + 0x30 .equ RCC_AHB2ENR , RCC_BASE + 0x34 .equ RCC_APB1ENR , RCC_BASE + 0x40 .equ RCC_APB2ENR , RCC_BASE + 0x44 .equ HSERDY , BIT17 .equ HSEON , BIT16 @ USART1 on STM32F4 chips: pp. 1018 in RM0090 (dm00031020-stm*.pdf) (RM0090) .equ USART1_BASE , 0x40011000 .equ USART1_SR , USART1_BASE + 0x00 .equ USART1_DR , USART1_BASE + 0x04 .equ USART1_BRR , USART1_BASE + 0x08 .equ USART1_CR1 , USART1_BASE + 0x0C .equ USART1_CR2 , USART1_BASE + 0x10 .equ USART1_CR3 , USART1_BASE + 0x14 .equ USART1_GPTR , USART1_BASE + 0x18 .equ USART_CR1_UE,BIT13 .equ USART_CR1_TE,BIT3 .equ USART_CR1_RE,BIT2 .ltorg .pool @ GPIO register map is similiar to STM32F4 chips. @ -> register boundary address pp. 65 in DM00031020.pdf .equ GPIOE_BASE , 0x40021000 .equ GPIOE_MODER , GPIOE_BASE + 0x00 @ pp. 287 of DM00031020.pdf .equ GPIOE_OTYPER , GPIOE_BASE + 0x04 .equ GPIOE_ODR , GPIOE_BASE + 0x14 .equ GPIOB_BASE, 0x40020400 .equ GPIOB_MODER , GPIOB_BASE + 0x00 @<<<<< .equ GPIOB_AFRL , GPIOB_BASE + 0x20 @<<<<< .equ GPIOB_AFRH , GPIOB_BASE + 0x24 .equ GPIOA_BASE , 0x40020000 .equ GPIOA_MODER , GPIOA_BASE + 0x00 .equ GPIOA_OTYPER , GPIOA_BASE + 0x04 .equ GPIOA_OSPEEDR , GPIOA_BASE + 0x08 .equ GPIOA_PUPDR , GPIOA_BASE + 0x0C .equ GPIOA_IDR , GPIOA_BASE + 0x10 .equ GPIOA_ODR , GPIOA_BASE + 0x14 .equ GPIOA_BSRR , GPIOA_BASE + 0x18 .equ GPIOA_LCKR , GPIOA_BASE + 0x1C .equ GPIOA_AFRL , GPIOA_BASE + 0x20 .equ GPIOA_AFRH , GPIOA_BASE + 0x24 .equ HSERDY , BIT17 .equ HSEON , BIT16 .equ USART_CR1_UE,BIT13 .equ USART_CR1_TE,BIT3 .equ USART_CR1_RE,BIT2 .equ RamAnfang, 0x20000000 @ Start of RAM Porting: Change this ! .equ returnstackanfang,RamAnfang+0x400 .pool .text .org 0 @ Common vector table for all Cortex M3/M4 targets .word returnstackanfang @ 00: Stack top address .word Reset+1 @ 01: Reset Vector +1 wegen des Thumb-Einsprunges .word faulthandler+1 @ 02: The NMI handler .word faulthandler+1 @ 03: The hard fault handler .word faulthandler+1 @ 04: The MPU fault handler .word faulthandler+1 @ 05: The bus fault handler .word faulthandler+1 @ 06: The usage fault handler .word 0 @ 07: Reserved .word 0 @ 08: Reserved .word 0 @ 09: Reserved .word 0 @ 10: Reserved .word nullhandler+1 @ 11: SVCall handler .word nullhandler+1 @ 12: Debug monitor handler .word 0 @ 13: Reserved .word nullhandler+1 @ 14: The PendSV handler .word irq_vektor_systick+1 @ 15: The SysTick handler @ Bis hierhin ist die Interruptvektortabelle bei allen ARM Cortex Chips gleich. @ Danach geht es mit den Besonderheiten eines jeden Chips los. .org 0x0400 .global Setup_UART,Setup_Clocks,Reset Reset: bl uart_init 1: movs r0,r0 b 1b @ ----------------------------------------------------------------------------- uart_init: @ ----------------------------------------------------------------------------- push {lr} bl Setup_Clocks bl Setup_UART pop {lr} bx lr nullhandler: faulthandler: irq_vektor_systick: 1: nop b 1b .ltorg @ store constants here @ @ ----------------------------------------------------------------------------- Setup_Clocks: @ ----------------------------------------------------------------------------- @ Initialize STM32 Clocks @ Ideally, we would just take the defaults to begin with and @ do nothing. Because it is possible that HSI is not @ accurate enough for the serial communication (USART3), we @ will switch from the internal 8 MHz clock (HSI) to the @ external 8 MHz clock (HSE). ldr r1, = RCC_CR mov r0, HSEON str r0, [r1] @ turn on the external clock awaitHSE: ldr r0, [r1] ands r0, #HSERDY beq.n awaitHSE @ hang here until external clock is stable @ at this point, the HSE is running and stable but I suppose we have not yet @ switched Sysclk to use it. ldr r1, = RCC_CFGR mov r0, # 1 str r0, [r1] @ switch to the external clock @ Turn off the HSION bit ldr r1, = RCC_CR ldr r0, [r1] and r0, 0xFFFFFFFE @ Zero the 0th bit str r0, [r1] bx lr @ ----------------------------------------------------------------------------- Setup_UART: @ ----------------------------------------------------------------------------- @ Turn on the clocks for all GPIOs. ldr r1, = RCC_AHB1ENR @ p. 242 und p. 266 manual RM00090 (Rev 18) @ dm00031020-stm32f405-415-stm32f407......pdf ldr r0, = BIT20+0x1f @ Enable Port A,B,C,D,E str r0, [r1] @ Set PORTB pins 10 and 11 in alternate function mode ldr r1, = GPIOB_MODER ldr r0, = 0x00A00280 @ 00000280 is Reset value for Port B, and @ switch PB10 and PB11 to alternate function str r0, [r1] @ Set alternate function 1 to enable USART3 pins on Port B ldr r1, = GPIOB_AFRH ldr r0, = 0x00007700 @ Alternate function 1 for TX and RX pins of @ USART3 on PORTB PB10 PB11 (pp. 272) str r0, [r1] @ Turn on the clock for USART3. ldr r1, = RCC_APB1ENR movs r0, #0x00400000 @ USART3EN str r0, [r1] @ Configure BRR by deviding the bus clock with the baud rate ldr r1, = USART3_BRR movs r0, #0x46 @ 115200 bps, ein ganz kleines bisschen langsamer... str r0, [r1] @ Enable the USART, TX, and RX circuit ldr r1, =USART3_CR1 ldr r0, =USART_CR1_UE+USART_CR1_TE+USART_CR1_RE @ str r0, [r1] ldr r1,=USART3_DR movs r0,#'X' str r0,[r1] @ Enable PE0 (User Led) to sink mode output and switch on ldr r1, = GPIOE_MODER ldr r0, = 0x01 @ bit PE0 to GP Output str r0,[r1] ldr r1,= GPIOE_OTYPER @ p. 281 ldr r0, = 0x01 @ open-drain str r0,[r1] ldr r1,= GPIOE_ODR @ LED ON ldr r0, = 0x0 str r0,[r1] bx lr .ltorg .end