# Reading C:/altera/13.1/modelsim_ase/tcl/vsim/pref.tcl 
# do watch_run_msim_rtl_vhdl.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Modifying C:\altera\13.1\modelsim_ase\win32aloem/../modelsim.ini
# 
# vcom -93 -work work {C:/altera/13.1/Uebungen/ProjectOne/Digital-Time-Clock/watch.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity watch
# -- Compiling architecture beh_watch of watch
# 
rtl.do
# invalid command name "rtl.do"
do rtl.do
# Cannot open macro file: rtl.do
do rtl_do
# Cannot open macro file: rtl_do
do rtl.do
# Cannot open macro file: rtl.do
do rtl.do
# Cannot open macro file: rtl.do
do rtl.do
# Cannot open macro file: rtl.do
vsim work.watch(beh_watch)
# vsim work.watch(beh_watch) 
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.watch(beh_watch)
do rtl.do
# Cannot open macro file: rtl.do
add wave -position end  sim:/watch/CLK
add wave -position end  sim:/watch/Reset
add wave -position end  sim:/watch/sec
add wave -position end  sim:/watch/Min0
add wave -position end  sim:/watch/Min1
add wave -position end  sim:/watch/Hr0
add wave -position end  sim:/watch/Hr1
add wave -position end  sim:/watch/Divider
add wave -position end  sim:/watch/CLK_ena
do rtl.do
# Cannot open macro file: rtl.do
do rtl.do
# Cannot open macro file: rtl.do
write format wave -window .main_pane.wave.interior.cs.body.pw.wf C:/altera/13.1/Uebungen/ProjectOne/Digital-Time-Clock/simulation/modelsim/wave.do
do rtl.do
# Cannot open macro file: rtl.do
do rtl_work
# Cannot open macro file: rtl_work
