library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity pwm2 is 
	port(
			CLK : in	std_logic;
			SW5 : in std_logic;
			SW4 : in std_logic;
			SW3 : in std_logic;
			SW2 : in std_logic;
			SW1 : in std_logic;
			SW0 : in std_logic;
			PWM_Value : in integer range 0 to 255;
			PWM : out std_logic;
			Out2 : out std_logic);
	end pwm2;
	
	architecture Beh_pwm2 of pwm2 is
	signal count: integer range 0 to 255 := 255;
	signal treshold: integer range 0 to 255 := 0;
	--signal speed: integer range 0 to 255;
	begin
		Motor: process (all)
					begin
						if rising_edge (CLK) then
							Out2 <= '0';
							PWM <= '0';
								if count = treshold then
									PWM <= '0';
								end if;
									if count = 255 then
									   count <= 1;
										PWM <= '1';
										--Treshold <= PWM_Value;
											if PWM_Value = 0 then
											   PWM <= '0';
												Out2 <= '0';
											end if;
									else 
										count <= count+1;
									end if;
												if SW1 = '1' then
													PWM <= '1';
												end if;
													if SW0 = '1' then
														Out2 <= '1';
													end if;
														if SW2 = '1' then
															treshold <= 50;
														elsif SW3 = '1' then
															treshold <= 100;
														elsif SW4 = '1' then
																treshold <= 150;
														elsif SW5 = '1' then	
																treshold <= 250;
														end if;
						end if;
				end process;
			end beh_pwm2;
			
	--architecture Beh_pwm2 of pwm2 is
		--signal CLK_ena : std_logic; -- Enable Signal mit 1 MHz Frequenz
		--signal Divider : std_logic_vector(28 downto 0); -- Zähler für 1 MHz Enable Signal
		--signal Counter : std_logic_vector(3 downto 0); -- Zähler auf 1 MHz Basis
	--begin
		--ClkDiv1: process (all)
		--begin
			--if rising_edge (CLK) then
				--Divider <= Divider + 1; 			-- erhöhe Divider Counter 
															-- Dazu  use ieee.std_logic_unsigned.all; einbinden
				--if Divider = 25000000 then 			-- falls Divider = 49 (und jetzt auf 50 erhöht wurde): 
					--Divider <= (others => '0'); 		-- Divider = 0
				--end if; 
					--if Divider = 0 then -- falls Divider = 0 
						--CLK_ena <= '1'; -- setze enable high für 1 G_Clk Periode
					--else
						--CLK_ena <= '0'; -- sonst setze enable low
					--end if; 
			--end if; -- end if rising edge
	--end process ClkDiv1;
				
				
				
				
	--Motor: process (all)
			--begin
				--if rising_edge(CLK) then -- Globaler Clock: Steigende G_Clk Flanke(50MHz): 
					--if CLK_ena = '1' then -- ist 1 für eine G_Clk Periode 
						--Counter <= Counter + '1'; -- Inkrementiere Counter 
						--if Counter = x"9" then -- falls Counter = 10 (am Ende des Prozesses)
							--Counter <= x"0"; -- Counter = 0
						--end if; 
							--Out2 <= '0';
							--PWM <= '0';
								--if SW1 = '1' then
									--PWM <= '1';
								--end if;
									--if SW0 = '1' then
										--Out2 <= '1';
									--end if;
					--end if;
				--end if;
		--end process;
	--end beh_pwm2;