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-- Company: 
-- Engineer: 
-- 
-- Create Date:    06:48:06 06/22/2022 
-- Design Name: 
-- Module Name:    pwm2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity pwm2 is 
   port( CLK :       IN  std_logic;
         SW  :       IN  std_logic_vector (5 downto 0);
         PWM_Value : IN  std_logic_vector (7 downto 0);
         PWM :       OUT   std_logic;
         Out2 :      OUT  std_logic);
end pwm2;


architecture Beh_pwm2 of pwm2 is
   signal count:    integer range 0 to 255 := 255;
   signal treshold: integer range 0 to 255 := 0;
begin

    Motor: process (CLK)
    begin
      if rising_edge (CLK) then

         if count = treshold then
            PWM <= '0';
         end if;

         if count = 255 then
            count <= 1;
            PWM <= '1';
            if unsigned(PWM_Value) = 0 then -- naja, eigenartige Abfrage...
               PWM <= '0';
            end if;
         else 
            count <= count+1;
         end if;

         if SW(1) = '1' then
            PWM <= '1';
         end if;

        
         if    SW(2) = '1' then     treshold <= 50;
         elsif SW(3) = '1' then     treshold <= 100;
         elsif SW(4) = '1' then     treshold <= 150;
         elsif SW(5) = '1' then     treshold <= 250;
         end if;

         -- für später mal:
         -- Treshold <= PWM_Value;

      end if;
   end process;


   Out2 <= SW(0); 

end beh_pwm2;