LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY tb_pwm2 IS
END tb_pwm2;
 
ARCHITECTURE behavior OF tb_pwm2 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT pwm2
    PORT(
         CLK :       IN  std_logic;
         SW  :       IN  std_logic_vector (5 downto 0);
         PWM_Value : IN  std_logic_vector (7 downto 0);
         PWM :       OUT std_logic;
         Out2 :      OUT std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal SW  : std_logic_vector (5 downto 0) := "000000";
   signal PWM_Value : std_logic_vector (7 downto 0) := "10000000";

 	--Outputs
   signal PWM : std_logic;
   
   signal Out2 : std_logic;

BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: pwm2 PORT MAP (
          CLK => CLK,
          SW => SW,
          PWM_Value => PWM_Value,
          PWM => PWM,
          Out2 => Out2
        );

   CLK <= not CLK after 1 us;
 
   sw(0) <= not sw(0) after 222 ms;
   
   sw(1) <= not sw(1) after 333 ms;

   -- Stimulus process
   stim_proc: process
   begin		

      wait for 10 ms;
      sw(5 downto 2) <= "0001"; 
      
      wait for 10 ms;
      sw(5 downto 2) <= "0010"; 

      wait for 10 ms;
      sw(5 downto 2) <= "0100"; 

      wait for 10 ms;
      sw(5 downto 2) <= "1000"; 

      wait for 10 ms;
      sw(5 downto 2) <= "0101"; 

      wait for 10 ms;
      sw(5 downto 2) <= "1010"; 

      wait;
   end process;

END;