LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_watch IS
END tb_watch;
 
ARCHITECTURE behavior OF tb_watch IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT watch
    PORT(
         CLK : IN  std_logic;
         Reset : IN  std_logic;
         sec : OUT  std_logic;
         Min0 : OUT  std_logic_vector(6 downto 0);
         Min1 : OUT  std_logic_vector(6 downto 0);
         Hr0 : OUT  std_logic_vector(6 downto 0);
         Hr1 : OUT  std_logic_vector(6 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal Reset : std_logic := '1';

 	--Outputs
   signal sec : std_logic;
   signal Min0 : std_logic_vector(6 downto 0);
   signal Min1 : std_logic_vector(6 downto 0);
   signal Hr0 : std_logic_vector(6 downto 0);
   signal Hr1 : std_logic_vector(6 downto 0);


BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: watch PORT MAP (
          CLK => CLK,
          Reset => Reset,
          sec => sec,
          Min0 => Min0,
          Min1 => Min1,
          Hr0 => Hr0,
          Hr1 => Hr1
        );

 	CLK <= not CLK after 10 us; -- Simulation schneller mit 50kHz Takt 
  
   Reset <= '0' after 10 ms;
END;