FEATURES

High-Performance Architecture
 Single 8051 Instruction Cycle in 54ns
 DC to 75MHz Clock Rate
 Flat 16MB Address Space
 Four Data Pointers with Auto-Increment/Decrement and Select-Accelerate Data Movement
 16/32-Bit Math Accelerator

Multitiered Networking and I/O
 10/100 Ethernet Media Access Controller (MAC)
 CAN 2.0B Controller
 1-Wire Net Controller
 Three Full-Duplex Hardware Serial Ports
 Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O Pins)

Robust ROM Firmware
 Supports Network Boot Over Ethernet Using DHCP and TFTP
 Full, Application-Accessible TCP/IP Network Stack
 Supports IPv4 and IPv6
 Implements UDP, TCP, DHCP, ICMP, and IGMP
 Preemptive, Priority-Based Task Scheduler
 MAC Address can Optionally be Acquired from IEEERegistered
 DS2502-E48

10/100 Ethernet Mac
 Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC (10Mbps) Interfaces Allow Selection of PHY
 Low-Power Operation
 Ultra-Low-Power Sleep Mode with Magic Packet™ and Wake-Up Frame Detection
 8kB On-Chip Tx/Rx Packet Data Memory with Buffer
 Control Unit Reduces Load on CPU
 Half- or Full-Duplex Operation with Flow Control
 Multicast/Broadcast Address Filtering with VLAN Support

Full-Function CAN 2.0B Controller
 15 Message Centers
 Supports Standard (11-Bit) and Extended (29-Bit) Identifiers and Global Masks
 Media Byte Filtering to Support DeviceNet™, SDS, and Higher Layer CAN Protocols
 Auto-Baud Mode and SIESTA Low-Power Mode

Integrated Primary System Logic
 16 Total Interrupt Sources with Six External
 Four 16-Bit Timer/Counters
 2x/4x Clock Multiplier Reduces Electromagnetic
 Interference (EMI)
 Programmable Watchdog Timer
 Oscillator-Fail Detection
 Programmable IrDA Clock

Advanced Power Management
 Energy Saving 1.8V Core
 3.3V I/O Operation, 5V Tolerant
 Power-Management, Idle, and Stop Mode
 Operations with Switchback Feature
 Ethernet and CAN Shutdown Control for Power Conservation
 Early Warning Power-Fail Interrupt
 Power-Fail Reset

Enhanced Memory Architecture
 Selectable 8/10-Bit Stack Pointer for High-Level Language Support
 1kB Additional On-Chip SRAM Usable as Stack/Data Memory
 16-Bit/24-Bit Paged/24-Bit Contiguous Modes
 Selectable Multiplexed/Nonmultiplexed External Memory Interface
 Merged Program/Data Memory Space Allows In-System Programming
 Defaults to True 8051-Memory Compatibility