library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity MUX_0 is
	port
	(
		i_Signal1                      : in    std_logic; 
		i_Signal2                      : in    std_logic;
		i_Error                        : in    std_logic;
		i_Ready                        : in    std_logic;
		o_Out                          : out   std_logic 
	);
end MUX_0;

architecture rtl of MUX_0 is

begin

	o_Out <= '0' when (i_Ready = '0' and i_Error = '0') else
	   i_Signal2 when (i_Ready = '0' and i_Error = '1') else
	   i_Signal1 when (i_Ready = '1' and i_Error = '0') else
	   i_Signal2 when (i_Ready = '1' and i_Error = '1');

end;