library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity MUX_1 is
	port
	(
		i_Signal1                      : in    std_logic; 
		i_Signal2                      : in    std_logic;
		i_Error                        : in    std_logic;
		i_Ready                        : in    std_logic;
		o_Out                          : out   std_logic 
	);
end MUX_1;

architecture rtl of MUX_1 is

begin

	process(i_Signal1, i_Signal2, i_Error, i_Ready)
	begin
		if i_Error = '0' then
			if i_Ready = '0' then
				o_Out <= '0';
			else
				o_Out <= i_Signal1;
			end if;
		else
			o_Out <= i_Signal2;
		end if;
	end process;

end;