library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MUX_2 is port ( i_Signal1 : in std_logic; i_Signal2 : in std_logic; i_Error : in std_logic; i_Ready : in std_logic; o_Out : out std_logic ); end MUX_2; architecture rtl of MUX_2 is signal s_vector : std_logic_vector(1 downto 0) := "00"; begin s_vector <= i_Error & i_Ready; with s_vector select o_Out <= '0' when "00", i_Signal1 when "01", i_Signal2 when others; end;