library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity MUX_TOP is
	port
	(
		i_Signal1                      : in    std_logic; 
		i_Signal2                      : in    std_logic;
		i_Error                        : in    std_logic;
		i_Ready                        : in    std_logic;
		o_Out                          : out   std_logic_vector(2 downto 0) 
	);
end MUX_TOP;

architecture rtl of MUX_TOP is

begin

	inst_MUX_0 : entity work.MUX_0
		port map
		(
			i_Signal1                      => i_Signal1,
			i_Signal2                      => i_Signal2,
			i_Error                        => i_Error,
			i_Ready                        => i_Ready,
			o_Out                          => o_Out(0)
		);

	inst_MUX_1 : entity work.MUX_1
		port map
		(
			i_Signal1                      => i_Signal1,
			i_Signal2                      => i_Signal2,
			i_Error                        => i_Error,
			i_Ready                        => i_Ready,
			o_Out                          => o_Out(1)
		);

	inst_MUX_2 : entity work.MUX_2
		port map
		(
			i_Signal1                      => i_Signal1,
			i_Signal2                      => i_Signal2,
			i_Error                        => i_Error,
			i_Ready                        => i_Ready,
			o_Out                          => o_Out(2)
		);

end;