library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TB_MUX is
end TB_MUX;

architecture tb of TB_MUX is

signal s_lfsr                          : std_logic_vector(31 downto 0) := (others => '0');

signal s_Signal1                       : std_logic := '0';
signal s_Signal2                       : std_logic := '0';
signal s_Error                         : std_logic := '0';
signal s_Ready                         : std_logic := '0';
signal s_Out                           : std_logic_vector(2 downto 0) := (others => '0');

begin

	process begin
		s_lfsr    <= s_lfsr(30 downto 0) & not(s_lfsr(31) xor s_lfsr(22) xor s_lfsr(2) xor s_lfsr(1));
		s_Signal1 <= s_lfsr(3);
		s_Signal2 <= s_lfsr(5);
		s_Error   <= s_lfsr(8);
		s_Ready   <= s_lfsr(12);
		wait for 10 ns;
	end process;

	inst_MUX_TOP : entity work.MUX_TOP
		port map
		(
			i_Signal1                      => s_Signal1,
			i_Signal2                      => s_Signal2,
			i_Error                        => s_Error,
			i_Ready                        => s_Ready,
			o_Out                          => s_Out
		);

end;