--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: Counter.vhd
-- File history:
--      <Revision number>: <Date>: <Comments>
--      <Revision number>: <Date>: <Comments>
--      <Revision number>: <Date>: <Comments>
--
-- Description: 
--
-- Eventcounter zur Impulszaehlung
--
--   ---- Ports ----
-- reset:    asynchroner Reseteingang, Low-Aktiv
-- clk:      Systemtakt zum Eintakten der Signale
-- Count:    Impulseingang. Die Impulse werden bei steigender Taktflanke von clk eingetaktet, muessen daher eine Impulsbreite von mindestens 1/clk haben
-- timebase: Zeitbasis. Bei 1 werden Impulse am Eingeng gezaehlt. 
--
-- Targeted device: <Family::IGLOO2> <Die::M2GL010> <Package::144 TQ>
-- Author: M
--
--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;

entity Counter is
port (
    --<port_name> : <direction> <type>;
	clk : IN  std_logic;
    reset : IN std_logic;
	Count : IN  std_logic; 
    timebase : IN std_logic;
    
    rd : IN std_logic;
    busif : OUT std_logic_vector(15 downto 0) 
);
end Counter;

architecture architecture_Counter of Counter is
	signal cnt : integer range 0 to 65535 ; --16 bit
    signal count_processed : std_logic ;
    signal outputbuffer : std_logic_vector(15 downto 0); 
    signal buffer_filled : std_logic ;

begin
   -- architecture body
  event_counter : process (clk, reset, Count, count_processed, outputbuffer, timebase, buffer_filled)
  begin
    if reset='0' then 
      cnt <= 0;
      count_processed <= '0';
      buffer_filled <= '0';
      outputbuffer <= (others => '0');
    else
      if clk = '1' and clk'event then
          --increment counter
          if timebase = '1' then
            if Count='1' then
              if count_processed='0' then
                cnt <= cnt +1;
                count_processed <= '1';
              end if;
            else
              count_processed <= '0';
            end if; -- Count=1
            buffer_filled <='0' ;
          else    -- timebase=0
            if buffer_filled='0' then
              outputbuffer <= std_logic_vector(to_unsigned(cnt, 16));
              buffer_filled <='1' ;
            end if;
          end if; -- timebase=0
      end if; --clk
      
      if clk = '0' and clk'event then
        if buffer_filled='1' then
          cnt <= 0;
        end if; 
      end if;
    end if; --reset
  end process;


  readout : process (clk, rd, busif, outputbuffer, reset)
  begin
    if reset='0' then 
      busif <= (others => 'Z');
    else
      if clk = '1' and clk'event then
        if rd='1' then
          busif <= outputbuffer ;
        else
          busif <= (others => 'Z'); 
        end if;      
      end if;
    end if;
  end process;

end architecture_Counter;