--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: Timebase.vhd
-- File history:
--      <Revision number>: <Date>: <Comments>
--      <Revision number>: <Date>: <Comments>
--      <Revision number>: <Date>: <Comments>
--
-- Description: 
--
-- <Description here>
--
-- Targeted device: <Family::IGLOO2> <Die::M2GL010> <Package::144 TQ>
-- Author: M. Latzel
--
--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

entity Timebase is

 generic ( TEILFAKTOR : natural := 2000000); -- Berechnung: gewuenschte Zeitbasis furch Periodendauer der Haupttaktes
                                             -- also z.B.: 100ms bei 20MHz -->  0.1/0.00000005 bzw. 100/0.00005 ->  2000000

port (
    --<port_name> : <direction> <type>;
	clk : IN  std_logic; 
	timebase : OUT  std_logic
);
end Timebase;

architecture architecture_Timebase of Timebase is
  signal timer :integer range 0 to 20000000; -- bis 20 MHz
begin
   -- architecture body
   tb : process (clk)
   begin
     if clk='1' and clk'event then
        if timer < TEILFAKTOR then
          timer <= timer +1;
          timebase <= '1';
        else
          timebase <= '0';
--          if timer < (TEILFAKTOR+1) then
--            timer <= timer +1;
--          else  
            timer <= 0;
--          end if;
        end if;
     end if;
   end process;

end architecture_Timebase;