-------------------------------------------------------------------------------- -- Company: -- -- File: Counter.vhd -- File history: -- : : -- : : -- : : -- -- Description: -- -- Eventcounter zur Impulszaehlung -- -- ---- Ports ---- -- reset: asynchroner Reseteingang, Low-Aktiv -- clk: Systemtakt zum Eintakten der Signale -- Count: Impulseingang. Die Impulse werden bei steigender Taktflanke von clk eingetaktet, muessen daher eine Impulsbreite von mindestens 1/clk haben -- timebase: Zeitbasis. Bei 1 werden Impulse am Eingeng gezaehlt. -- -- Targeted device: -- Author: M -- -------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; entity Counter is port ( -- : ; clk : IN std_logic; reset : IN std_logic; Count : IN std_logic; timebase : IN std_logic; rd : IN std_logic; busif : OUT std_logic_vector(15 downto 0) ); end Counter; architecture architecture_Counter of Counter is -- signal count_processed : std_logic ; -- signal buffer_filled : std_logic ; signal count_0_int : std_logic ; signal count_int : std_logic ; signal cnt : integer range 0 to 65535 ; --16 bit signal outputbuffer : std_logic_vector(15 downto 0); type states is(wait_for_count, count_recognized, door_closed, buffer_uptodate); signal state : states ; begin sync : process (clk) begin if clk = '1' and clk'event then count_0_int <= Count; count_int <= count_0_int; end if; end process; -- architecture body event_counter : process (clk, reset) begin if reset='0' then cnt <= 0; outputbuffer <= (others => '0'); state <= wait_for_count ; else if clk = '1' and clk'event then case state is when wait_for_count => if timebase ='0' then state <= door_closed ; else if count_int = '1' then state <= count_recognized ; cnt <= cnt +1; end if; end if; when count_recognized => if timebase ='0' then state <= door_closed ; else if count_int = '0' then state <= wait_for_count ; end if; end if; when door_closed => outputbuffer <= std_logic_vector(to_unsigned(cnt, 16)); state <= buffer_uptodate ; when buffer_uptodate => cnt <= 0; if timebase ='1' then if count_int = '1' then state <= count_recognized ; -- Impulse beim uebergang ignorieren else state <= wait_for_count ; end if; end if; -- when others => state <= wait_for_count ; end case; end if; -- rising edge end if; --reset end process; readout : process (clk, rd, busif, outputbuffer, reset) begin if reset='0' then busif <= (others => 'Z'); else if clk = '1' and clk'event then if rd='1' then busif <= outputbuffer ; else busif <= (others => 'Z'); end if; end if; end if; end process; end architecture_Counter;