library ieee;
use ieee.std_logic_1164.all;


entity counter_tb is
end entity counter_tb;

architecture testbench of counter_tb is

    signal simulation_run   : boolean   := true;
    constant clk_frequency  : natural   := 10000000;
    constant clk_period     : time      := 1 sec / clk_frequency;

    signal tb_clk           : std_logic := '0';
    signal tb_reset         : std_logic := '0';
    signal tb_Count         : std_logic := '0';
    signal tb_timebase      : std_logic := '1';
    signal tb_rd            : std_logic := '0';
    signal tb_busif         : std_logic_vector(15 downto 0);

begin

    tb_clk      <= not tb_clk after clk_period / 2 when simulation_run;
    tb_reset    <= '0', '1' after 5 * clk_period;

    tb_timebase <= '0' after 24 us, '1' after 25 us;

    tb_Count    <= '1' after  5 us, '0' after 5.1 us, 
                   '1' after 10 us, '0' after 11 us, 
                   '1' after 15 us, '0' after 17 us;

    dut: entity work.Counter 
    port map 
    (
        clk      => tb_clk,      -- : in std_logic;
        reset    => tb_reset,    -- : in std_logic;
        Count    => tb_Count,    -- : in std_logic;
        timebase => tb_timebase, -- : in std_logic;
        --
        rd       => tb_rd,       -- : in  std_logic;
        busif    => tb_busif     -- : out std_logic_vector(15 downto 0)
    );


    main: process
    begin
        wait for 30 us;
        simulation_run <= false;
        report "Simulation ends.";
        wait;
    end process;

end architecture;