typedef unsigned char io_byte;
typedef unsigned int io_word;
typedef unsigned long io_dword;
typedef unsigned long io_dlong[2];

#include "banks.h"
#define FKT1_TYPE bank0
#define FKT2_TYPE bank0
#define FKT3_TYPE bank0
#define FKT4_TYPE bank0

/*------------------------------------------------------------------------------------
  Processor Mode Register 0
------------------------------------------------------------------------------------*/
typedef union PM0_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte PM03:1;		/* Software reset bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} PM0;
#define		PM0		(*(volatile union PM0_T *) 0x0004)

/*------------------------------------------------------------------------------------
  Processor Mode Register 1
------------------------------------------------------------------------------------*/
typedef union PM1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte PM12:1;		/* WDT interrupt/reset switch bit */
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} PM1;
#define		PM1		(*(volatile union PM1_T *) 0x0005)

/*------------------------------------------------------------------------------------
  System Clock Control Register 0
------------------------------------------------------------------------------------*/
typedef union CM0_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte CM02:1;		/* Wait mode peripheral function clock stop bit */
		io_byte B3:1;
		io_byte B4:1;
		io_byte CM05:1;		/* Xin clock (Xin-Xout) stop bit */
		io_byte CM06:1;		/* CPU clock division select bit0 */
		io_byte B7:1;
	} BIT;
} CM0;
#define		CM0		(*(volatile union CM0_T *) 0x0006)

/*------------------------------------------------------------------------------------
  System Clock Control Register 1
------------------------------------------------------------------------------------*/
typedef union CM1_T
{
	io_byte REG;
	struct
	{
		io_byte CM10:1;		/* All clock stop control bit */
		io_byte CM11:1;		/* XIN-XOUT on-chip feedback resistor select bit */
		io_byte B2:1;
		io_byte CM13:1;		/* Port/Xin-Xout switch bit */
		io_byte CM14:1;		/* Low-speed on-chip oscillator stop bit */
		io_byte B5:1;
		io_byte CM16:1;		/* CPU clock division select bit1 */
		io_byte CM17:1;		/* CPU clock division select bit1 */
	} BIT;
} CM1;
#define		CM1		(*(volatile union CM1_T *) 0x0007)

/*------------------------------------------------------------------------------------
  Module Standby Control Register
------------------------------------------------------------------------------------*/
typedef union MSTCR_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte MSTIIC:1;		/* SSU standby bit */
		io_byte MSTTRD:1;		/* Timer RD standby bit */
		io_byte MSTTRC:1;		/* Timer RC standby bit */
		io_byte MSTTRG:1;		/* Timer RG standby bit */
		io_byte B7:1;
	} BIT;
} MSTCR;
#define		MSTCR		(*(volatile union MSTCR_T *) 0x0008)

/*------------------------------------------------------------------------------------
  System Clock Control Register 3
------------------------------------------------------------------------------------*/
typedef union CM3_T
{
	io_byte REG;
	struct
	{
		io_byte CM30:1;		/* WAIT control bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte CM35:1;		/* CPU clock division when exiting wait mode select bit */
		io_byte CM36:1;		/* System clock when exiting wait mode or stop mode select bit */
		io_byte CM37:1;		/* System clock when exiting wait mode or stop mode select bit */
	} BIT;
} CM3;
#define		CM3		(*(volatile union CM3_T *) 0x0009)

/*------------------------------------------------------------------------------------
  High-Speed On-Chip Oscillator Control Register 7
------------------------------------------------------------------------------------*/
typedef union FRA7_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} FRA7;
#define		FRA7		(*(volatile union FRA7_T *) 0x0015)

/*------------------------------------------------------------------------------------
  Protect Register
------------------------------------------------------------------------------------*/
typedef union PRCR_T
{
	io_byte REG;
	struct
	{
		io_byte PRC0:1;		/* Protect bit0 */
		io_byte PRC1:1;		/* Protect bit1 */
		io_byte PRC2:1;		/* Protect bit2 */
		io_byte PRC3:1;		/* Protect bit3 */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} PRCR;
#define		PRCR		(*(volatile union PRCR_T *) 0x000A)

/*------------------------------------------------------------------------------------
  Reset Source Determination Register
------------------------------------------------------------------------------------*/
typedef union RSTFR_T
{
	io_byte REG;
	struct
	{
		io_byte CWR:1;		/* Cold start-up/warm start-up determine flag */
		io_byte HWR:1;		/* Hardware reset detect flag */
		io_byte SWR:1;		/* Software reset detect flag */
		io_byte WDR:1;		/* Watchdog timer reset detect flag */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} RSTFR;
#define		RSTFR		(*(volatile union RSTFR_T *) 0x000B)

/*------------------------------------------------------------------------------------
  Oscillation Stop Detection Register
------------------------------------------------------------------------------------*/
typedef union OCD_T
{
	io_byte REG;
	struct
	{
		io_byte OCD0:1;		/* Oscillation stop detection enable bit */
		io_byte OCD1:1;		/* Oscillation stop detection interrupt enable bit */
		io_byte OCD2:1;		/* System clock select bit */
		io_byte OCD3:1;		/* Clock monitor bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} OCD;
#define		OCD		(*(volatile union OCD_T *) 0x000C)

/*------------------------------------------------------------------------------------
  Watchdog Timer Reset Register
------------------------------------------------------------------------------------*/
typedef union WDTR_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} WDTR;
#define		WDTR		(*(volatile union WDTR_T *) 0x000D)

/*------------------------------------------------------------------------------------
  Watchdog Timer Start Register
------------------------------------------------------------------------------------*/
typedef union WDTS_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} WDTS;
#define		WDTS		(*(volatile union WDTS_T *) 0x000E)

/*------------------------------------------------------------------------------------
  Watchdog Timer Control Register
------------------------------------------------------------------------------------*/
typedef union WDTC_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte WDTC7:1;		/* Prescaler select bit */
	} BIT;
} WDTC;
#define		WDTC		(*(volatile union WDTC_T *) 0x000F)

/*------------------------------------------------------------------------------------
  Count Source Protection Mode Register
------------------------------------------------------------------------------------*/
typedef union CSPR_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte CSPRO:1;		/* Count source protection mode select bit */
	} BIT;
} CSPR;
#define		CSPR		(*(volatile union CSPR_T *) 0x001C)

/*------------------------------------------------------------------------------------
  High-Speed On-Chip Oscillator Control Register 0
------------------------------------------------------------------------------------*/
typedef union FRA0_T
{
	io_byte REG;
	struct
	{
		io_byte FRA00:1;		/* High-speed on-chip oscillator enable bit */
		io_byte FRA01:1;		/* High-speed on-chip oscillator select bit */
		io_byte B2:1;
		io_byte FRA03:1;		/* fOCO128 clock select bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} FRA0;
#define		FRA0		(*(volatile union FRA0_T *) 0x0023)

/*------------------------------------------------------------------------------------
  High-Speed On-Chip Oscillator Control Register 1
------------------------------------------------------------------------------------*/
typedef union FRA1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} FRA1;
#define		FRA1		(*(volatile union FRA1_T *) 0x0024)

/*------------------------------------------------------------------------------------
  High-Speed On-Chip Oscillator Control Register 2
------------------------------------------------------------------------------------*/
typedef union FRA2_T
{
	io_byte REG;
	struct
	{
		io_byte FRA20:1;		/* High-speed on-chip oscillator frequency switching bit */
		io_byte FRA21:1;		/* High-speed on-chip oscillator frequency switching bit */
		io_byte FRA22:1;		/* High-speed on-chip oscillator frequency switching bit */
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} FRA2;
#define		FRA2		(*(volatile union FRA2_T *) 0x0025)

/*------------------------------------------------------------------------------------
  On-Chip Reference Voltage Control Register
------------------------------------------------------------------------------------*/
typedef union OCVREFCR_T
{
	io_byte REG;
	struct
	{
		io_byte OCVREFAN:1;		/* On-chip reference voltage to analog input connect bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} OCVREFCR;
#define		OCVREFCR		(*(volatile union OCVREFCR_T *) 0x0026)

/*------------------------------------------------------------------------------------
  High-Speed On-Chip Oscillator Control Register 4
------------------------------------------------------------------------------------*/
typedef union FRA4_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} FRA4;
#define		FRA4		(*(volatile union FRA4_T *) 0x0029)

/*------------------------------------------------------------------------------------
  High-Speed On-Chip Oscillator Control Register 5
------------------------------------------------------------------------------------*/
typedef union FRA5_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} FRA5;
#define		FRA5		(*(volatile union FRA5_T *) 0x002A)

/*------------------------------------------------------------------------------------
  High-Speed On-Chip Oscillator Control Register 6
------------------------------------------------------------------------------------*/
typedef union FRA6_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} FRA6;
#define		FRA6		(*(volatile union FRA6_T *) 0x002B)

/*------------------------------------------------------------------------------------
  High-Speed On-Chip Oscillator Control Register 3
------------------------------------------------------------------------------------*/
typedef union FRA3_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} FRA3;
#define		FRA3		(*(volatile union FRA3_T *) 0x002F)

/*------------------------------------------------------------------------------------
  Voltage Monitor Circuit Control Register
------------------------------------------------------------------------------------*/
typedef union CMPA_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte IRQ1SEL:1;		/* Voltage monitor 1 interrupt type select bit */
		io_byte IRQ2SEL:1;		/* Voltage monitor 2 interrupt type select bit */
		io_byte B6:1;
		io_byte COMPSEL:1;		/* Voltage monitor interrupt type selection enable bit */
	} BIT;
} CMPA;
#define		CMPA		(*(volatile union CMPA_T *) 0x0030)

/*------------------------------------------------------------------------------------
  Voltage Monitor Circuit Edge Select Register
------------------------------------------------------------------------------------*/
typedef union VCAC_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte VCAC1:1;		/* Voltage monitor 1 circuit edge select bit */
		io_byte VCAC2:1;		/* Voltage monitor 2 circuit edge select bit */
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} VCAC;
#define		VCAC		(*(volatile union VCAC_T *) 0x0031)

/*------------------------------------------------------------------------------------
  Voltage Detect Register 1
------------------------------------------------------------------------------------*/
typedef union VCA1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte VCA13:1;		/* Voltage detection 2 signal monitor flag */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} VCA1;
#define		VCA1		(*(volatile union VCA1_T *) 0x0033)

/*------------------------------------------------------------------------------------
  Voltage Detect Register 2
------------------------------------------------------------------------------------*/
typedef union VCA2_T
{
	io_byte REG;
	struct
	{
		io_byte VCA20:1;		/* Internal power low consumption enable bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte VCA25:1;		/* Voltage detection 0 enable bit */
		io_byte VCA26:1;		/* Voltage detection 1 enable bit */
		io_byte VCA27:1;		/* Voltage detection 2 enable bit */
	} BIT;
} VCA2;
#define		VCA2		(*(volatile union VCA2_T *) 0x0034)

/*------------------------------------------------------------------------------------
  Voltage Detection 1 Level Select Register
------------------------------------------------------------------------------------*/
typedef union VD1LS_T
{
	io_byte REG;
	struct
	{
		io_byte VD1S0:1;		/* Voltage detection 1 Level select bit */
		io_byte VD1S1:1;		/* Voltage detection 1 Level select bit */
		io_byte VD1S2:1;		/* Voltage detection 1 Level select bit */
		io_byte VD1S3:1;		/* Voltage detection 1 Level select bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} VD1LS;
#define		VD1LS		(*(volatile union VD1LS_T *) 0x0036)

/*------------------------------------------------------------------------------------
  Voltage Monitor 0 Circuit Control Register
------------------------------------------------------------------------------------*/
typedef union VW0C_T
{
	io_byte REG;
	struct
	{
		io_byte VW0C0:1;		/* Voltage monitor 0 reset enable bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} VW0C;
#define		VW0C		(*(volatile union VW0C_T *) 0x0038)

/*------------------------------------------------------------------------------------
  Voltage Monitor 1 Circuit Control Register
------------------------------------------------------------------------------------*/
typedef union VW1C_T
{
	io_byte REG;
	struct
	{
		io_byte VW1C0:1;		/* Voltage monitor 1 interrupt enable bit */
		io_byte VW1C1:1;		/* Voltage monitor 1 digital filter disable mode select bit */
		io_byte VW1C2:1;		/* Voltage change detection flag */
		io_byte VW1C3:1;		/* Voltage detection 1 signal monitor flag */
		io_byte VW1F0:1;		/* Sampling clock select bit */
		io_byte VW1F1:1;		/* Sampling clock select bit */
		io_byte B6:1;
		io_byte VW1C7:1;		/* Voltage monitor 1 interrupt generating condition select bit */
	} BIT;
} VW1C;
#define		VW1C		(*(volatile union VW1C_T *) 0x0039)

/*------------------------------------------------------------------------------------
  Voltage Monitor 2 Circuit Control Register
------------------------------------------------------------------------------------*/
typedef union VW2C_T
{
	io_byte REG;
	struct
	{
		io_byte VW2C0:1;		/* Voltage monitor 2 interrupt enable bit */
		io_byte VW2C1:1;		/* Voltage monitor 2 digital filter disabled mode select bit */
		io_byte VW2C2:1;		/* Voltage change detection flag */
		io_byte VW2C3:1;		/* WDT detection monitor flag */
		io_byte VW2F0:1;		/* Sampling clock select bit */
		io_byte VW2F1:1;		/* Sampling clock select bit */
		io_byte B6:1;
		io_byte VW2C7:1;		/* Voltage monitor 2 interrupt generating condition select bit */
	} BIT;
} VW2C;
#define		VW2C		(*(volatile union VW2C_T *) 0x003A)

/*------------------------------------------------------------------------------------
  DTC Activation Control Register
------------------------------------------------------------------------------------*/
typedef union DTCTL_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte NMIF:1;		/* Non-maskable interrupt generation bit */
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCTL;
#define		DTCTL		(*(volatile union DTCTL_T *) 0x0080)

/*------------------------------------------------------------------------------------
  DTC Activation Enable Register 0
------------------------------------------------------------------------------------*/
typedef union DTCEN0_T
{
	io_byte REG;
	struct
	{
		io_byte DTCEN00:1;		/* DTC activation enable bit */
		io_byte DTCEN01:1;		/* DTC activation enable bit */
		io_byte DTCEN02:1;		/* DTC activation enable bit */
		io_byte DTCEN03:1;		/* DTC activation enable bit */
		io_byte DTCEN04:1;		/* DTC activation enable bit */
		io_byte DTCEN05:1;		/* DTC activation enable bit */
		io_byte DTCEN06:1;		/* DTC activation enable bit */
		io_byte DTCEN07:1;		/* DTC activation enable bit */
	} BIT;
} DTCEN0;
#define		DTCEN0		(*(volatile union DTCEN0_T *) 0x0088)

/*------------------------------------------------------------------------------------
  DTC Activation Enable Register 1
------------------------------------------------------------------------------------*/
typedef union DTCEN1_T
{
	io_byte REG;
	struct
	{
		io_byte DTCEN10:1;		/* DTC activation enable bit */
		io_byte DTCEN11:1;		/* DTC activation enable bit */
		io_byte DTCEN12:1;		/* DTC activation enable bit */
		io_byte DTCEN13:1;		/* DTC activation enable bit */
		io_byte DTCEN14:1;		/* DTC activation enable bit */
		io_byte DTCEN15:1;		/* DTC activation enable bit */
		io_byte DTCEN16:1;		/* DTC activation enable bit */
		io_byte DTCEN17:1;		/* DTC activation enable bit */
	} BIT;
} DTCEN1;
#define		DTCEN1		(*(volatile union DTCEN1_T *) 0x0089)

/*------------------------------------------------------------------------------------
  DTC Activation Enable Register 2
------------------------------------------------------------------------------------*/
typedef union DTCEN2_T
{
	io_byte REG;
	struct
	{
		io_byte DTCEN20:1;		/* DTC activation enable bit */
		io_byte DTCEN21:1;		/* DTC activation enable bit */
		io_byte DTCEN22:1;		/* DTC activation enable bit */
		io_byte DTCEN23:1;		/* DTC activation enable bit */
		io_byte DTCEN24:1;		/* DTC activation enable bit */
		io_byte DTCEN25:1;		/* DTC activation enable bit */
		io_byte DTCEN26:1;		/* DTC activation enable bit */
		io_byte DTCEN27:1;		/* DTC activation enable bit */
	} BIT;
} DTCEN2;
#define		DTCEN2		(*(volatile union DTCEN2_T *) 0x008A)

/*------------------------------------------------------------------------------------
  DTC Activation Enable Register 3
------------------------------------------------------------------------------------*/
typedef union DTCEN3_T
{
	io_byte REG;
	struct
	{
		io_byte DTCEN30:1;		/* DTC activation enable bit */
		io_byte DTCEN31:1;		/* DTC activation enable bit */
		io_byte DTCEN32:1;		/* DTC activation enable bit */
		io_byte DTCEN33:1;		/* DTC activation enable bit */
		io_byte DTCEN34:1;		/* DTC activation enable bit */
		io_byte DTCEN35:1;		/* DTC activation enable bit */
		io_byte DTCEN36:1;		/* DTC activation enable bit */
		io_byte DTCEN37:1;		/* DTC activation enable bit */
	} BIT;
} DTCEN3;
#define		DTCEN3		(*(volatile union DTCEN3_T *) 0x008B)

/*------------------------------------------------------------------------------------
  DTC Activation Enable Register 4
------------------------------------------------------------------------------------*/
typedef union DTCEN4_T
{
	io_byte REG;
	struct
	{
		io_byte DTCEN40:1;		/* DTC activation enable bit */
		io_byte DTCEN41:1;		/* DTC activation enable bit */
		io_byte DTCEN42:1;		/* DTC activation enable bit */
		io_byte DTCEN43:1;		/* DTC activation enable bit */
		io_byte DTCEN44:1;		/* DTC activation enable bit */
		io_byte DTCEN45:1;		/* DTC activation enable bit */
		io_byte DTCEN46:1;		/* DTC activation enable bit */
		io_byte DTCEN47:1;		/* DTC activation enable bit */
	} BIT;
} DTCEN4;
#define		DTCEN4		(*(volatile union DTCEN4_T *) 0x008C)

/*------------------------------------------------------------------------------------
  DTC Activation Enable Register 5
------------------------------------------------------------------------------------*/
typedef union DTCEN5_T
{
	io_byte REG;
	struct
	{
		io_byte DTCEN50:1;		/* DTC activation enable bit */
		io_byte DTCEN51:1;		/* DTC activation enable bit */
		io_byte DTCEN52:1;		/* DTC activation enable bit */
		io_byte DTCEN53:1;		/* DTC activation enable bit */
		io_byte DTCEN54:1;		/* DTC activation enable bit */
		io_byte DTCEN55:1;		/* DTC activation enable bit */
		io_byte DTCEN56:1;		/* DTC activation enable bit */
		io_byte DTCEN57:1;		/* DTC activation enable bit */
	} BIT;
} DTCEN5;
#define		DTCEN5		(*(volatile union DTCEN5_T *) 0x008D)

/*------------------------------------------------------------------------------------
  DTC Activation Enable Register 6
------------------------------------------------------------------------------------*/
typedef union DTCEN6_T
{
	io_byte REG;
	struct
	{
		io_byte DTCEN60:1;		/* DTC activation enable bit */
		io_byte DTCEN61:1;		/* DTC activation enable bit */
		io_byte DTCEN62:1;		/* DTC activation enable bit */
		io_byte DTCEN63:1;		/* DTC activation enable bit */
		io_byte DTCEN64:1;		/* DTC activation enable bit */
		io_byte DTCEN65:1;		/* DTC activation enable bit */
		io_byte DTCEN66:1;		/* DTC activation enable bit */
		io_byte DTCEN67:1;		/* DTC activation enable bit */
	} BIT;
} DTCEN6;
#define		DTCEN6		(*(volatile union DTCEN6_T *) 0x008E)

/*------------------------------------------------------------------------------------
  Timer RF Register, Capture and Compare 0 Register, Compare 1 Register
------------------------------------------------------------------------------------*/
typedef union TRF_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRF;
#define		TRF		(*(volatile union TRF_T *) 0x0090)

/*------------------------------------------------------------------------------------
  Timer RF Register, Capture and Compare 0 Register, Compare 1 Register
------------------------------------------------------------------------------------*/
typedef union TRFM0_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRFM0;
#define		TRFM0		(*(volatile union TRFM0_T *) 0x009C)

/*------------------------------------------------------------------------------------
  Timer RF Register, Capture and Compare 0 Register, Compare 1 Register
------------------------------------------------------------------------------------*/
typedef union TRFM1_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRFM1;
#define		TRFM1		(*(volatile union TRFM1_T *) 0x009E)

/*------------------------------------------------------------------------------------
  Timer RF Control Register 0
------------------------------------------------------------------------------------*/
typedef union TRFCR0_T
{
	io_byte REG;
	struct
	{
		io_byte TSTART:1;		/* Timer RF count start bit */
		io_byte TCK0:1;		/* Timer RF count source select bit */
		io_byte TCK1:1;		/* Timer RF count source select bit */
		io_byte TRFC03:1;		/* Capture polarity select bit */
		io_byte TRFC04:1;		/* Capture polarity select bit */
		io_byte TRFC05:1;		/* CMP output select bit 0 when count stops */
		io_byte TRFC06:1;		/* CMP output select bit 1 when count stops */
		io_byte B7:1;
	} BIT;
} TRFCR0;
#define		TRFCR0		(*(volatile union TRFCR0_T *) 0x009A)

/*------------------------------------------------------------------------------------
  Timer RF Control Register 1
------------------------------------------------------------------------------------*/
typedef union TRFCR1_T
{
	io_byte REG;
	struct
	{
		io_byte TIPF0:1;		/* TRFI filter select bit */
		io_byte TIPF1:1;		/* TRFI filter select bit */
		io_byte CCLR:1;		/* TRF register count operation select bit */
		io_byte TMOD:1;		/* Timer RF operation mode select bit */
		io_byte TRFC14:1;		/* Compare 0 output seelct bit */
		io_byte TRFC15:1;		/* Compare 0 output seelct bit */
		io_byte TRFC16:1;		/* Compare 1 output seelct bit */
		io_byte TRFC17:1;		/* Compare 1 output seelct bit */
	} BIT;
} TRFCR1;
#define		TRFCR1		(*(volatile union TRFCR1_T *) 0x009B)

/*------------------------------------------------------------------------------------
  UART0 Bit Rate Register
------------------------------------------------------------------------------------*/
typedef union U0BRG_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} U0BRG;
#define		U0BRG		(*(volatile union U0BRG_T *) 0x00A1)

/*------------------------------------------------------------------------------------
  UART2 Bit Rate Register
------------------------------------------------------------------------------------*/
typedef union U2BRG_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} U2BRG;
#define		U2BRG		(*(volatile union U2BRG_T *) 0x00A9)

/*------------------------------------------------------------------------------------
  UART2 Degital Filter Function Select Register
------------------------------------------------------------------------------------*/
typedef union URXDF_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte DF2EN:1;		/* RXD2 digital filter enable bit */
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} URXDF;
#define		URXDF		(*(volatile union URXDF_T *) 0x00B0)

/*------------------------------------------------------------------------------------
  UART2 Special Mode Register 5
------------------------------------------------------------------------------------*/
typedef union U2SMR5_T
{
	io_byte REG;
	struct
	{
		io_byte MP:1;		/* Multiprocessor Communication enable bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte MPIE:1;		/* Multiprocessor Communication control bit */
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} U2SMR5;
#define		U2SMR5		(*(volatile union U2SMR5_T *) 0x00BB)

/*------------------------------------------------------------------------------------
  UART2 Special Mode Register 4
------------------------------------------------------------------------------------*/
typedef union U2SMR4_T
{
	io_byte REG;
	struct
	{
		io_byte STAREQ:1;		/* Start condition generate bit */
		io_byte RSTAREQ:1;		/* Restart condition generate bit */
		io_byte STPREQ:1;		/* Stop condition generate bit */
		io_byte STSPSEL:1;		/* SCL, SDA output select bit */
		io_byte ACKD:1;		/* ACK data bit */
		io_byte ACKC:1;		/* ACK data output enable bit */
		io_byte SCLHI:1;		/* SCL stop enable bit */
		io_byte SWC9:1;		/* SCL wait bit 3 */
	} BIT;
} U2SMR4;
#define		U2SMR4		(*(volatile union U2SMR4_T *) 0x00BC)

/*------------------------------------------------------------------------------------
  UART2 Special Mode Register 3
------------------------------------------------------------------------------------*/
typedef union U2SMR3_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte CKPH:1;		/* Clock phase set bit */
		io_byte B2:1;
		io_byte NODC:1;		/* Clock output select bit */
		io_byte B4:1;
		io_byte DL0:1;		/* SDA2 digital delay setup bit */
		io_byte DL1:1;		/* SDA2 digital delay setup bit */
		io_byte DL2:1;		/* SDA2 digital delay setup bit */
	} BIT;
} U2SMR3;
#define		U2SMR3		(*(volatile union U2SMR3_T *) 0x00BD)

/*------------------------------------------------------------------------------------
  UART2 Special Mode Register 2
------------------------------------------------------------------------------------*/
typedef union U2SMR2_T
{
	io_byte REG;
	struct
	{
		io_byte IICM2:1;		/* I2C mode select bit 2 */
		io_byte CSC:1;		/* Clock synchronization bit */
		io_byte SWC:1;		/* SCL wait output bit */
		io_byte B3:1;
		io_byte STAC:1;		/* UART2 initialization bit */
		io_byte SWC2:1;		/* SCL wait output bit 2 */
		io_byte SDHI:1;		/* SDA output disabled bit */
		io_byte B7:1;
	} BIT;
} U2SMR2;
#define		U2SMR2		(*(volatile union U2SMR2_T *) 0x00BE)

/*------------------------------------------------------------------------------------
  UART2 Special Mode Register
------------------------------------------------------------------------------------*/
typedef union U2SMR_T
{
	io_byte REG;
	struct
	{
		io_byte IICM:1;		/* I2C mode select bit */
		io_byte B1:1;
		io_byte BBS:1;		/* Bus busy flag */
		io_byte B3:1;
		io_byte ABSCS:1;		/* Bus collision detect sampling clock select bit */
		io_byte ACSE:1;		/* Auto clear function select bit of transmit enable bit */
		io_byte SSS:1;		/* Transmit satart condition select bit */
		io_byte B7:1;
	} BIT;
} U2SMR;
#define		U2SMR		(*(volatile union U2SMR_T *) 0x00BF)

/*------------------------------------------------------------------------------------
  A/D Mode Register
------------------------------------------------------------------------------------*/
typedef union ADMOD_T
{
	io_byte REG;
	struct
	{
		io_byte CKS0:1;		/* Division select bit */
		io_byte CKS1:1;		/* Division select bit */
		io_byte CKS2:1;		/* Clock source select bit */
		io_byte MD0:1;		/* A/D operating mode select bit */
		io_byte MD1:1;		/* A/D operating mode select bit */
		io_byte MD2:1;		/* A/D operating mode select bit */
		io_byte ADCAP0:1;		/* A/D Conversion trigger select bit */
		io_byte ADCAP1:1;		/* A/D Conversion trigger select bit */
	} BIT;
} ADMOD;
#define		ADMOD		(*(volatile union ADMOD_T *) 0x00D4)

/*------------------------------------------------------------------------------------
  A/D Input Select Register
------------------------------------------------------------------------------------*/
typedef union ADINSEL_T
{
	io_byte REG;
	struct
	{
		io_byte CH0:1;		/* Analog input pin select bit */
		io_byte CH1:1;		/* Analog input pin select bit */
		io_byte CH2:1;		/* Analog input pin select bit */
		io_byte B3:1;
		io_byte SCAN0:1;		/* A/D sweep pin count select bit */
		io_byte SCAN1:1;		/* A/D sweep pin count select bit */
		io_byte ADGSEL0:1;		/* A/D input group select bit */
		io_byte ADGSEL1:1;		/* A/D input group select bit */
	} BIT;
} ADINSEL;
#define		ADINSEL		(*(volatile union ADINSEL_T *) 0x00D5)

/*------------------------------------------------------------------------------------
  A/D Control Register 0
------------------------------------------------------------------------------------*/
typedef union ADCON0_T
{
	io_byte REG;
	struct
	{
		io_byte ADST:1;		/* A/D conversion start flag */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} ADCON0;
#define		ADCON0		(*(volatile union ADCON0_T *) 0x00D6)

/*------------------------------------------------------------------------------------
  A/D Control Register1
------------------------------------------------------------------------------------*/
typedef union ADCON1_T
{
	io_byte REG;
	struct
	{
		io_byte ADEX0:1;		/* Extended analog input select bit */
		io_byte ADEX1:1;		/* Extended analog input select bit */
		io_byte ADEX2:1;		/* Extended analog input select bit */
		io_byte B3:1;
		io_byte BITS:1;		/* 8/10-bit mode select bit */
		io_byte ADSTBY:1;		/* A/D standby bit */
		io_byte ADDDAEN:1;		/* A/D open-circuit detection assist function enable bit */
		io_byte ADDDAEL:1;		/* A/D open-circuit detection assist method select bit */
	} BIT;
} ADCON1;
#define		ADCON1		(*(volatile union ADCON1_T *) 0x00D7)

/*------------------------------------------------------------------------------------
  Port P0 Register
------------------------------------------------------------------------------------*/
typedef union P0_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P00 bit */
		io_byte _1:1;		/* Port P01 bit */
		io_byte _2:1;		/* Port P02 bit */
		io_byte _3:1;		/* Port P03 bit */
		io_byte _4:1;		/* Port P04 bit */
		io_byte _5:1;		/* Port P05 bit */
		io_byte _6:1;		/* Port P06 bit */
		io_byte _7:1;		/* Port P07 bit */
	} BIT;
} P0;
#define		P0		(*(volatile union P0_T *) 0x00E0)

/*------------------------------------------------------------------------------------
  Port P1 Direction Register
------------------------------------------------------------------------------------*/
typedef union PD0_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P00 direction bit */
		io_byte _1:1;		/* Port P01 direction bit */
		io_byte _2:1;		/* Port P02 direction bit */
		io_byte _3:1;		/* Port P03 direction bit */
		io_byte _4:1;		/* Port P04 direction bit */
		io_byte _5:1;		/* Port P05 direction bit */
		io_byte _6:1;		/* Port P06 direction bit */
		io_byte _7:1;		/* Port P07 direction bit */
	} BIT;
} PD0;
#define		PD0		(*(volatile union PD0_T *) 0x00E2)

/*------------------------------------------------------------------------------------
  Port P1 Register
------------------------------------------------------------------------------------*/
typedef union P1_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P10 bit */
		io_byte _1:1;		/* Port P11 bit */
		io_byte _2:1;		/* Port P12 bit */
		io_byte _3:1;		/* Port P13 bit */
		io_byte _4:1;		/* Port P14 bit */
		io_byte _5:1;		/* Port P15 bit */
		io_byte _6:1;		/* Port P16 bit */
		io_byte _7:1;		/* Port P17 bit */
	} BIT;
} P1;
#define		P1		(*(volatile union P1_T *) 0x00E1)

/*------------------------------------------------------------------------------------
  Port P1 Direction Register
------------------------------------------------------------------------------------*/
typedef union PD1_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P10 direction bit */
		io_byte _1:1;		/* Port P11 direction bit */
		io_byte _2:1;		/* Port P12 direction bit */
		io_byte _3:1;		/* Port P13 direction bit */
		io_byte _4:1;		/* Port P14 direction bit */
		io_byte _5:1;		/* Port P15 direction bit */
		io_byte _6:1;		/* Port P16 direction bit */
		io_byte _7:1;		/* Port P17 direction bit */
	} BIT;
} PD1;
#define		PD1		(*(volatile union PD1_T *) 0x00E3)

/*------------------------------------------------------------------------------------
  Port P2 Register
------------------------------------------------------------------------------------*/
typedef union P2_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P20 bit */
		io_byte _1:1;		/* Port P21 bit */
		io_byte _2:1;		/* Port P22 bit */
		io_byte _3:1;		/* Port P23 bit */
		io_byte _4:1;		/* Port P24 bit */
		io_byte _5:1;		/* Port P25 bit */
		io_byte _6:1;		/* Port P26 bit */
		io_byte _7:1;		/* Port P27 bit */
	} BIT;
} P2;
#define		P2		(*(volatile union P2_T *) 0x00E4)

/*------------------------------------------------------------------------------------
  Port P2 Direction Register
------------------------------------------------------------------------------------*/
typedef union PD2_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P20 direction bit */
		io_byte _1:1;		/* Port P21 direction bit */
		io_byte _2:1;		/* Port P22 direction bit */
		io_byte _3:1;		/* Port P23 direction bit */
		io_byte _4:1;		/* Port P24 direction bit */
		io_byte _5:1;		/* Port P25 direction bit */
		io_byte _6:1;		/* Port P26 direction bit */
		io_byte _7:1;		/* Port P27 direction bit */
	} BIT;
} PD2;
#define		PD2		(*(volatile union PD2_T *) 0x00E6)

/*------------------------------------------------------------------------------------
  Port P3 Register
------------------------------------------------------------------------------------*/
typedef union P3_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P30 bit */
		io_byte _1:1;		/* Port P31 bit */
		io_byte _2:1;		/* Port P32 bit */
		io_byte _3:1;		/* Port P33 bit */
		io_byte _4:1;		/* Port P34 bit */
		io_byte _5:1;		/* Port P35 bit */
		io_byte _6:1;		/* Port P36 bit */
		io_byte _7:1;		/* Port P37 bit */
	} BIT;
} P3;
#define		P3		(*(volatile union P3_T *) 0x00E5)

/*------------------------------------------------------------------------------------
  Port P3 Direction Register
------------------------------------------------------------------------------------*/
typedef union PD3_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P30 direction bit */
		io_byte _1:1;		/* Port P31 direction bit */
		io_byte _2:1;		/* Port P32 direction bit */
		io_byte _3:1;		/* Port P33 direction bit */
		io_byte _4:1;		/* Port P34 direction bit */
		io_byte _5:1;		/* Port P35 direction bit */
		io_byte _6:1;		/* Port P36 direction bit */
		io_byte _7:1;		/* Port P37 direction bit */
	} BIT;
} PD3;
#define		PD3		(*(volatile union PD3_T *) 0x00E7)

/*------------------------------------------------------------------------------------
  Port P4 Register
------------------------------------------------------------------------------------*/
typedef union P4_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte _2:1;		/* Port P42 bit */
		io_byte _3:1;		/* Port P43 bit */
		io_byte _4:1;		/* Port P44 bit */
		io_byte _5:1;		/* Port P45 bit */
		io_byte _6:1;		/* Port P46 bit */
		io_byte _7:1;		/* Port P47 bit */
	} BIT;
} P4;
#define		P4		(*(volatile union P4_T *) 0x00E8)

/*------------------------------------------------------------------------------------
  Port P5 Register
------------------------------------------------------------------------------------*/
typedef union P5_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P50 bit */
		io_byte _1:1;		/* Port P51 bit */
		io_byte _2:1;		/* Port P52 bit */
		io_byte _3:1;		/* Port P53 bit */
		io_byte _4:1;		/* Port P54 bit */
		io_byte B5:1;
		io_byte _6:1;		/* Port P56 bit */
		io_byte _7:1;		/* Port P57 bit */
	} BIT;
} P5;
#define		P5		(*(volatile union P5_T *) 0x00E9)

/*------------------------------------------------------------------------------------
  Port P4 Direction Register
------------------------------------------------------------------------------------*/
typedef union PD4_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte _3:1;		/* Port P43 direction bit */
		io_byte _4:1;		/* Port P44 direction bit */
		io_byte _5:1;		/* Port P45 direction bit */
		io_byte _6:1;		/* Port P46 direction bit */
		io_byte _7:1;		/* Port P47 direction bit */
	} BIT;
} PD4;
#define		PD4		(*(volatile union PD4_T *) 0x00EA)

/*------------------------------------------------------------------------------------
  Port P5 Direction Register
------------------------------------------------------------------------------------*/
typedef union PD5_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P50 direction bit */
		io_byte _1:1;		/* Port P51 direction bit */
		io_byte _2:1;		/* Port P52 direction bit */
		io_byte _3:1;		/* Port P53 direction bit */
		io_byte _4:1;		/* Port P54 direction bit */
		io_byte B5:1;
		io_byte _6:1;		/* Port P56 direction bit */
		io_byte _7:1;		/* Port P57 direction bit */
	} BIT;
} PD5;
#define		PD5		(*(volatile union PD5_T *) 0x00EB)

/*------------------------------------------------------------------------------------
  Port P6 Register
------------------------------------------------------------------------------------*/
typedef union P6_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P60 bit */
		io_byte _1:1;		/* Port P61 bit */
		io_byte _2:1;		/* Port P62 bit */
		io_byte _3:1;		/* Port P63 bit */
		io_byte _4:1;		/* Port P64 bit */
		io_byte _5:1;		/* Port P65 bit */
		io_byte _6:1;		/* Port P66 bit */
		io_byte _7:1;		/* Port P67 bit */
	} BIT;
} P6;
#define		P6		(*(volatile union P6_T *) 0x00EC)

/*------------------------------------------------------------------------------------
  Port P6 Direction Register
------------------------------------------------------------------------------------*/
typedef union PD6_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P60 direction bit */
		io_byte _1:1;		/* Port P61 direction bit */
		io_byte _2:1;		/* Port P62 direction bit */
		io_byte _3:1;		/* Port P63 direction bit */
		io_byte _4:1;		/* Port P64 direction bit */
		io_byte _5:1;		/* Port P65 direction bit */
		io_byte _6:1;		/* Port P66 direction bit */
		io_byte _7:1;		/* Port P67 direction bit */
	} BIT;
} PD6;
#define		PD6		(*(volatile union PD6_T *) 0x00EE)

/*------------------------------------------------------------------------------------
  Port P8 Register
------------------------------------------------------------------------------------*/
typedef union P8_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P80 bit */
		io_byte _1:1;		/* Port P81 bit */
		io_byte _2:1;		/* Port P82 bit */
		io_byte _3:1;		/* Port P83 bit */
		io_byte _4:1;		/* Port P84 bit */
		io_byte _5:1;		/* Port P85 bit */
		io_byte _6:1;		/* Port P86 bit */
		io_byte B7:1;
	} BIT;
} P8;
#define		P8		(*(volatile union P8_T *) 0x00F0)

/*------------------------------------------------------------------------------------
  Port P8 Direction Register
------------------------------------------------------------------------------------*/
typedef union PD8_T
{
	io_byte REG;
	struct
	{
		io_byte _0:1;		/* Port P80 direction bit */
		io_byte _1:1;		/* Port P81 direction bit */
		io_byte _2:1;		/* Port P82 direction bit */
		io_byte _3:1;		/* Port P83 direction bit */
		io_byte _4:1;		/* Port P84 direction bit */
		io_byte _5:1;		/* Port P85 direction bit */
		io_byte _6:1;		/* Port P86 direction bit */
		io_byte B7:1;
	} BIT;
} PD8;
#define		PD8		(*(volatile union PD8_T *) 0x00F2)

/*------------------------------------------------------------------------------------
  Timer RA0 Control Register
------------------------------------------------------------------------------------*/
typedef union TRA0CR_T
{
	io_byte REG;
	struct
	{
		io_byte TSTART:1;		/* Timer RA count start bit */
		io_byte TCSTF:1;		/* Timer RA count status flag */
		io_byte TSTOP:1;		/* Timer RA count forcible stop bit */
		io_byte B3:1;
		io_byte TEDGF:1;		/* Active edge judgment flag */
		io_byte TUNDF:1;		/* Timer RA underflow flag */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRA0CR;
#define		TRA0CR		(*(volatile union TRA0CR_T *) 0x0100)

/*------------------------------------------------------------------------------------
  Timer RA0 I/O Control Register
------------------------------------------------------------------------------------*/
typedef union TRA0IOC_T
{
	io_byte REG;
	struct
	{
		io_byte TEDGSEL:1;		/* TRAIO0 polarity switch bit */
		io_byte TOPCR:1;		/* TRAIO0 output control bit */
		io_byte TOENA:1;		/* TRAO0 output enable bit */
		io_byte TIOSEL:1;		/* Hardware LIN function select bit */
		io_byte TIPF0:1;		/* TRAIO0 input filter select bit */
		io_byte TIPF1:1;		/* TRAIO0 input filter select bit */
		io_byte TIOGT0:1;		/* TRAIO0 event input control bit */
		io_byte TIOGT1:1;		/* TRAIO0 event input control bit */
	} BIT;
} TRA0IOC;
#define		TRA0IOC		(*(volatile union TRA0IOC_T *) 0x0101)

/*------------------------------------------------------------------------------------
  Timer RA0 Mode Register
------------------------------------------------------------------------------------*/
typedef union TRA0MR_T
{
	io_byte REG;
	struct
	{
		io_byte TMOD0:1;		/* Timer RA operating mode select bit */
		io_byte TMOD1:1;		/* Timer RA operating mode select bit */
		io_byte TMOD2:1;		/* Timer RA operating mode select bit */
		io_byte B3:1;
		io_byte TCK0:1;		/* Timer RA count source select bit */
		io_byte TCK1:1;		/* Timer RA count source select bit */
		io_byte TCK2:1;		/* Timer RA count source select bit */
		io_byte TCKCUT:1;		/* Timer RA count source cutoff bit */
	} BIT;
} TRA0MR;
#define		TRA0MR		(*(volatile union TRA0MR_T *) 0x0102)

/*------------------------------------------------------------------------------------
  Timer RA0 Prescaler Register
------------------------------------------------------------------------------------*/
typedef union TRA0PRE_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRA0PRE;
#define		TRA0PRE		(*(volatile union TRA0PRE_T *) 0x0103)

/*------------------------------------------------------------------------------------
  Timer RA0 Register
------------------------------------------------------------------------------------*/
typedef union TRA0_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRA0;
#define		TRA0		(*(volatile union TRA0_T *) 0x0104)

/*------------------------------------------------------------------------------------
  LIN0 Control Register 2
------------------------------------------------------------------------------------*/
typedef union LIN0CR2_T
{
	io_byte REG;
	struct
	{
		io_byte BCE:1;		/* Bus collision detection during Sync Break transmission enable bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} LIN0CR2;
#define		LIN0CR2		(*(volatile union LIN0CR2_T *) 0x0105)

/*------------------------------------------------------------------------------------
  LIN0 Control Register
------------------------------------------------------------------------------------*/
typedef union LIN0CR_T
{
	io_byte REG;
	struct
	{
		io_byte SFIE:1;		/* Synch Field measurement-completed interrupt enable bit */
		io_byte SBIE:1;		/* Synch Break detection interrupt enable bit */
		io_byte BCIE:1;		/* Bus collision detection interrupt enable bit */
		io_byte RXDSF:1;		/* RxD0 input status flag */
		io_byte LSTART:1;		/* Synch Break detection start bit */
		io_byte SBE:1;		/* RxD0 input unmasking timing select bit */
		io_byte MST:1;		/* LIN operation mode setting bit */
		io_byte LINE:1;		/* LIN operation start bit */
	} BIT;
} LIN0CR;
#define		LIN0CR		(*(volatile union LIN0CR_T *) 0x0106)

/*------------------------------------------------------------------------------------
  LIN0 Status Register
------------------------------------------------------------------------------------*/
typedef union LIN0ST_T
{
	io_byte REG;
	struct
	{
		io_byte SFDCT:1;		/* Synch Field measurement-completed flag */
		io_byte SBDCT:1;		/* Synch Break detection flag */
		io_byte BCDCT:1;		/* Bus collision detection flag */
		io_byte B0CLR:1;		/* SFDCT bit clear bit */
		io_byte B1CLR:1;		/* SBDCT bit clear bit */
		io_byte B2CLR:1;		/* BCDCT bit clear bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} LIN0ST;
#define		LIN0ST		(*(volatile union LIN0ST_T *) 0x0107)

/*------------------------------------------------------------------------------------
  Timer RB Control Register
------------------------------------------------------------------------------------*/
typedef union TRBCR_T
{
	io_byte REG;
	struct
	{
		io_byte TSTART:1;		/* Timer RB count start bit */
		io_byte TCSTF:1;		/* Timer RB count status flag */
		io_byte TSTOP:1;		/* Timer RB count forcible stop bit */
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRBCR;
#define		TRBCR		(*(volatile union TRBCR_T *) 0x0108)

/*------------------------------------------------------------------------------------
  Timer RB One-Shot Control Register
------------------------------------------------------------------------------------*/
typedef union TRBOCR_T
{
	io_byte REG;
	struct
	{
		io_byte TOSST:1;		/* Timer RB one-shot start bit */
		io_byte TOSSP:1;		/* Timer RB one-shot stop bit */
		io_byte TOSSTF:1;		/* Timer RB one-shot status flag */
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRBOCR;
#define		TRBOCR		(*(volatile union TRBOCR_T *) 0x0109)

/*------------------------------------------------------------------------------------
  Timer RB I/O Control Register
------------------------------------------------------------------------------------*/
typedef union TRBIOC_T
{
	io_byte REG;
	struct
	{
		io_byte TOPL:1;		/* Timer RB output level select bit */
		io_byte TOCNT:1;		/* Timer RB output switch bit */
		io_byte INOSTG:1;		/* One-shot trigger control bit */
		io_byte INOSEG:1;		/* One-shot trigger polarity select bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRBIOC;
#define		TRBIOC		(*(volatile union TRBIOC_T *) 0x010A)

/*------------------------------------------------------------------------------------
  Timer RB Mode Register
------------------------------------------------------------------------------------*/
typedef union TRBMR_T
{
	io_byte REG;
	struct
	{
		io_byte TMOD0:1;		/* Timer RB operating mode select bit */
		io_byte TMOD1:1;		/* Timer RB operating mode select bit */
		io_byte B2:1;
		io_byte TWRC:1;		/* Timer RB write control bit */
		io_byte TCK0:1;		/* Timer RB count source select bit */
		io_byte TCK1:1;		/* Timer RB count source select bit */
		io_byte B6:1;
		io_byte TCKCUT:1;		/* Timer RB count source cutoff bit */
	} BIT;
} TRBMR;
#define		TRBMR		(*(volatile union TRBMR_T *) 0x010B)

/*------------------------------------------------------------------------------------
  Timer RB Prescaler Register
------------------------------------------------------------------------------------*/
typedef union TRBPRE_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRBPRE;
#define		TRBPRE		(*(volatile union TRBPRE_T *) 0x010C)

/*------------------------------------------------------------------------------------
  Timer RB Secondary Register
------------------------------------------------------------------------------------*/
typedef union TRBSC_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRBSC;
#define		TRBSC		(*(volatile union TRBSC_T *) 0x010D)

/*------------------------------------------------------------------------------------
  Timer RB Primary Register
------------------------------------------------------------------------------------*/
typedef union TRBPR_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRBPR;
#define		TRBPR		(*(volatile union TRBPR_T *) 0x010E)

/*------------------------------------------------------------------------------------
  Timer RA1 Control Register
------------------------------------------------------------------------------------*/
typedef union TRA1CR_T
{
	io_byte REG;
	struct
	{
		io_byte TSTART:1;		/* Timer RA count start bit */
		io_byte TCSTF:1;		/* Timer RA count status flag */
		io_byte TSTOP:1;		/* Timer RA count forcible stop bit */
		io_byte B3:1;
		io_byte TEDGF:1;		/* Active edge judgment flag */
		io_byte TUNDF:1;		/* Timer RA underflow flag */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRA1CR;
#define		TRA1CR		(*(volatile union TRA1CR_T *) 0x0110)

/*------------------------------------------------------------------------------------
  Timer RA1 I/O Control Register
------------------------------------------------------------------------------------*/
typedef union TRA1IOC_T
{
	io_byte REG;
	struct
	{
		io_byte TEDGSEL:1;		/* TRAIO1 polarity switch bit */
		io_byte TOPCR:1;		/* TRAIO1 output control bit */
		io_byte TOENA:1;		/* TRAO1 output enable bit */
		io_byte TIOSEL:1;		/* Hardware LIN function select bit */
		io_byte TIPF0:1;		/* TRAIO1 input filter select bit */
		io_byte TIPF1:1;		/* TRAIO1 input filter select bit */
		io_byte TIOGT0:1;		/* TRAIO1 event input control bit */
		io_byte TIOGT1:1;		/* TRAIO1 event input control bit */
	} BIT;
} TRA1IOC;
#define		TRA1IOC		(*(volatile union TRA1IOC_T *) 0x0111)

/*------------------------------------------------------------------------------------
  Timer RA1 Mode Register
------------------------------------------------------------------------------------*/
typedef union TRA1MR_T
{
	io_byte REG;
	struct
	{
		io_byte TMOD0:1;		/* Timer RA operating mode select bit */
		io_byte TMOD1:1;		/* Timer RA operating mode select bit */
		io_byte TMOD2:1;		/* Timer RA operating mode select bit */
		io_byte B3:1;
		io_byte TCK0:1;		/* Timer RA count source select bit */
		io_byte TCK1:1;		/* Timer RA count source select bit */
		io_byte TCK2:1;		/* Timer RA count source select bit */
		io_byte TCKCUT:1;		/* Timer RA count source cutoff bit */
	} BIT;
} TRA1MR;
#define		TRA1MR		(*(volatile union TRA1MR_T *) 0x0112)

/*------------------------------------------------------------------------------------
  Timer RA1 Prescaler Register
------------------------------------------------------------------------------------*/
typedef union TRA1PRE_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRA1PRE;
#define		TRA1PRE		(*(volatile union TRA1PRE_T *) 0x0113)

/*------------------------------------------------------------------------------------
  Timer RA1 Register
------------------------------------------------------------------------------------*/
typedef union TRA1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRA1;
#define		TRA1		(*(volatile union TRA1_T *) 0x0114)

/*------------------------------------------------------------------------------------
  LIN1 Control Register 2
------------------------------------------------------------------------------------*/
typedef union LIN1CR2_T
{
	io_byte REG;
	struct
	{
		io_byte BCE:1;		/* Bus collision detection during Sync Break transmission enable bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} LIN1CR2;
#define		LIN1CR2		(*(volatile union LIN1CR2_T *) 0x0115)

/*------------------------------------------------------------------------------------
  LIN1 Control Register
------------------------------------------------------------------------------------*/
typedef union LIN1CR_T
{
	io_byte REG;
	struct
	{
		io_byte SFIE:1;		/* Synch Field measurement-completed interrupt enable bit */
		io_byte SBIE:1;		/* Synch Break detection interrupt enable bit */
		io_byte BCIE:1;		/* Bus collision detection interrupt enable bit */
		io_byte RXDSF:1;		/* RxD0 input status flag */
		io_byte LSTART:1;		/* Synch Break detection start bit */
		io_byte SBE:1;		/* RxD0 input unmasking timing select bit */
		io_byte MST:1;		/* LIN operation mode setting bit */
		io_byte LINE:1;		/* LIN operation start bit */
	} BIT;
} LIN1CR;
#define		LIN1CR		(*(volatile union LIN1CR_T *) 0x0116)

/*------------------------------------------------------------------------------------
  LIN1 Status Register
------------------------------------------------------------------------------------*/
typedef union LIN1ST_T
{
	io_byte REG;
	struct
	{
		io_byte SFDCT:1;		/* Synch Field measurement-completed flag */
		io_byte SBDCT:1;		/* Synch Break detection flag */
		io_byte BCDCT:1;		/* Bus collision detection flag */
		io_byte B0CLR:1;		/* SFDCT bit clear bit */
		io_byte B1CLR:1;		/* SBDCT bit clear bit */
		io_byte B2CLR:1;		/* BCDCT bit clear bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} LIN1ST;
#define		LIN1ST		(*(volatile union LIN1ST_T *) 0x0117)

/*------------------------------------------------------------------------------------
  Timer RE Counter Data Register
------------------------------------------------------------------------------------*/
typedef union TRESEC_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRESEC;
#define		TRESEC		(*(volatile union TRESEC_T *) 0x0118)

/*------------------------------------------------------------------------------------
  Timer RE Compare Data Register
------------------------------------------------------------------------------------*/
typedef union TREMIN_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TREMIN;
#define		TREMIN		(*(volatile union TREMIN_T *) 0x0119)

/*------------------------------------------------------------------------------------
  Timer RE Control Register 1
------------------------------------------------------------------------------------*/
typedef union TRECR1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte TCSTF:1;		/* Timer RE count status flag */
		io_byte TOENA:1;		/* TREO pin output enable bit */
		io_byte B3:1;
		io_byte TRERST:1;		/* Timer RE reset bit */
		io_byte B5:1;
		io_byte B6:1;
		io_byte TSTART:1;		/* Timer RE count start bit */
	} BIT;
} TRECR1;
#define		TRECR1		(*(volatile union TRECR1_T *) 0x011C)

/*------------------------------------------------------------------------------------
  Timer RE Control Register 2
------------------------------------------------------------------------------------*/
typedef union TRECR2_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte COMIE:1;		/* Compare match interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRECR2;
#define		TRECR2		(*(volatile union TRECR2_T *) 0x011D)

/*------------------------------------------------------------------------------------
  Timer RE Count Source Select Register
------------------------------------------------------------------------------------*/
typedef union TRECSR_T
{
	io_byte REG;
	struct
	{
		io_byte RCS0:1;		/* Count source select bit */
		io_byte RCS1:1;		/* Count source select bit */
		io_byte RCS2:1;		/* 4-Bit counter select bit */
		io_byte RCS3:1;		/* Output compare mode enable bit */
		io_byte RCS4:1;		/* Clock output select bit */
		io_byte RCS5:1;		/* Clock output select bit */
		io_byte RCS6:1;		/* Clock output select bit */
		io_byte B7:1;
	} BIT;
} TRECSR;
#define		TRECSR		(*(volatile union TRECSR_T *) 0x011E)

/*------------------------------------------------------------------------------------
  Timer RC Mode Register
------------------------------------------------------------------------------------*/
typedef union TRCMR_T
{
	io_byte REG;
	struct
	{
		io_byte PWMB:1;		/* PWM mode of TRCIOB select bit */
		io_byte PWMC:1;		/* PWM mode of TRCIOC select bit */
		io_byte PWMD:1;		/* PWM mode of TRCIOD select bit */
		io_byte PWM2:1;		/* PWM2 mode select bit */
		io_byte BFC:1;		/* TRCGRC register function select bit */
		io_byte BFD:1;		/* TRCGRD register function select bit */
		io_byte B6:1;
		io_byte TSTART:1;		/* TRC count start bit */
	} BIT;
} TRCMR;
#define		TRCMR		(*(volatile union TRCMR_T *) 0x0120)

/*------------------------------------------------------------------------------------
  Timer RC Control Register 1
------------------------------------------------------------------------------------*/
typedef union TRCCR1_T
{
	io_byte REG;
	struct
	{
		io_byte TOA:1;		/* TRCIOA output level select bit */
		io_byte TOB:1;		/* TRCIOB output level select bit */
		io_byte TOC:1;		/* TRCIOC output level select bit */
		io_byte TOD:1;		/* TRCIOD output level select bit */
		io_byte TCK0:1;		/* Count source selection bit */
		io_byte TCK1:1;		/* Count source selection bit */
		io_byte TCK2:1;		/* Count source selection bit */
		io_byte CCLR:1;		/* TRC counter clear select bit */
	} BIT;
} TRCCR1;
#define		TRCCR1		(*(volatile union TRCCR1_T *) 0x0121)

/*------------------------------------------------------------------------------------
  Timer RC Interrupt Enable Register
------------------------------------------------------------------------------------*/
typedef union TRCIER_T
{
	io_byte REG;
	struct
	{
		io_byte IMIEA:1;		/* Input capture / compare match interrupt enable bit A */
		io_byte IMIEB:1;		/* Input capture / compare match interrupt enable bit B */
		io_byte IMIEC:1;		/* Input capture / compare match interrupt enable bit C */
		io_byte IMIED:1;		/* Input capture / compare match interrupt enable bit D */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte OVIE:1;		/* Overflow interrupt enable bit */
	} BIT;
} TRCIER;
#define		TRCIER		(*(volatile union TRCIER_T *) 0x0122)

/*------------------------------------------------------------------------------------
  Timer RC Status Register
------------------------------------------------------------------------------------*/
typedef union TRCSR_T
{
	io_byte REG;
	struct
	{
		io_byte IMFA:1;		/* Input capture / compare match flag A */
		io_byte IMFB:1;		/* Input capture / compare match flag B */
		io_byte IMFC:1;		/* Input capture / compare match flag C */
		io_byte IMFD:1;		/* Input capture / compare match flag D */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte OVF:1;		/* Overflow flag */
	} BIT;
} TRCSR;
#define		TRCSR		(*(volatile union TRCSR_T *) 0x0123)

/*------------------------------------------------------------------------------------
  Timer RC I/O Contorol Register 0
------------------------------------------------------------------------------------*/
typedef union TRCIOR0_T
{
	io_byte REG;
	struct
	{
		io_byte IOA0:1;		/* TRCGRA control bit */
		io_byte IOA1:1;		/* TRCGRA control bit */
		io_byte IOA2:1;		/* TRCGRA mode select bit */
		io_byte IOA3:1;		/* TRCGRA input capture input switch bit */
		io_byte IOB0:1;		/* TRCGRB control bit */
		io_byte IOB1:1;		/* TRCGRB control bit */
		io_byte IOB2:1;		/* TRCGRB mode select bit */
		io_byte B7:1;
	} BIT;
} TRCIOR0;
#define		TRCIOR0		(*(volatile union TRCIOR0_T *) 0x0124)

/*------------------------------------------------------------------------------------
  Timer RC I/O Contorol Register 1
------------------------------------------------------------------------------------*/
typedef union TRCIOR1_T
{
	io_byte REG;
	struct
	{
		io_byte IOC0:1;		/* TRCGRC control bit */
		io_byte IOC1:1;		/* TRCGRC control bit */
		io_byte IOC2:1;		/* TRCGRC mode select bit */
		io_byte IOC3:1;		/* TRCGRC register function select bit */
		io_byte IOD0:1;		/* TRCGRD control bit */
		io_byte IOD1:1;		/* TRCGRD control bit */
		io_byte IOD2:1;		/* TRCGRD mode select bit */
		io_byte IOD3:1;		/* TRCGRD register function select bit */
	} BIT;
} TRCIOR1;
#define		TRCIOR1		(*(volatile union TRCIOR1_T *) 0x0125)

/*------------------------------------------------------------------------------------
  Timer RC Control Register 2
------------------------------------------------------------------------------------*/
typedef union TRCCR2_T
{
	io_byte REG;
	struct
	{
		io_byte POLB:1;		/* PWM mode output level control bit B */
		io_byte POLC:1;		/* PWM mode output level control bit C */
		io_byte POLD:1;		/* PWM mode output level control bit D */
		io_byte B3:1;
		io_byte B4:1;
		io_byte CSEL:1;		/* TRC count operation select bit */
		io_byte TCEG0:1;		/* TRCTRG input edge select bit */
		io_byte TCEG1:1;		/* TRCTRG input edge select bit */
	} BIT;
} TRCCR2;
#define		TRCCR2		(*(volatile union TRCCR2_T *) 0x0130)

/*------------------------------------------------------------------------------------
  Timer RC Digital Filter Function Select Register
------------------------------------------------------------------------------------*/
typedef union TRCDF_T
{
	io_byte REG;
	struct
	{
		io_byte DFA:1;		/* TRCIOA pin digital filter function select bit */
		io_byte DFB:1;		/* TRCIOB pin digital filter function select bit */
		io_byte DFC:1;		/* TRCIOC pin digital filter function select bit */
		io_byte DFD:1;		/* TRCIOD pin digital filter function select bit */
		io_byte DFTRG:1;		/* TRCIOG pin digital filter function select bit */
		io_byte B5:1;
		io_byte DFCK0:1;		/* Clock select bits for digital filter function */
		io_byte DFCK1:1;		/* Clock select bits for digital filter function */
	} BIT;
} TRCDF;
#define		TRCDF		(*(volatile union TRCDF_T *) 0x0131)

/*------------------------------------------------------------------------------------
  Timer RC Output Master Enable Register
------------------------------------------------------------------------------------*/
typedef union TRCOER_T
{
	io_byte REG;
	struct
	{
		io_byte EA:1;		/* TRCIOA output disable bit */
		io_byte EB:1;		/* TRCIOB output disable bit */
		io_byte EC:1;		/* TRCIOC output disable bit */
		io_byte ED:1;		/* TRCIOD output disable bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte PTO:1;		/* INT0 of pulse output forced cutoff signal input enabled bit */
	} BIT;
} TRCOER;
#define		TRCOER		(*(volatile union TRCOER_T *) 0x0132)

/*------------------------------------------------------------------------------------
  Timer RC Trigger Control Register
------------------------------------------------------------------------------------*/
typedef union TRCADCR_T
{
	io_byte REG;
	struct
	{
		io_byte ADTRGAE:1;		/* A/D trigger A enable bit */
		io_byte ADTRGBE:1;		/* A/D trigger B enable bit */
		io_byte ADTRGCE:1;		/* A/D trigger C enable bit */
		io_byte ADTRGDE:1;		/* A/D trigger D enable bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRCADCR;
#define		TRCADCR		(*(volatile union TRCADCR_T *) 0x0133)

/*------------------------------------------------------------------------------------
  Timer RD Trigger Control Register
------------------------------------------------------------------------------------*/
typedef union TRDADCR_T
{
	io_byte REG;
	struct
	{
		io_byte ADTRGA0E:1;		/* A/D trigger A0 enable bit */
		io_byte ADTRGB0E:1;		/* A/D trigger B0 enable bit */
		io_byte ADTRGC0E:1;		/* A/D trigger C0 enable bit */
		io_byte ADTRGD0E:1;		/* A/D trigger D0 enable bit */
		io_byte ADTRGA1E:1;		/* A/D trigger A1 enable bit */
		io_byte ADTRGB1E:1;		/* A/D trigger B1 enable bit */
		io_byte ADTRGC1E:1;		/* A/D trigger C1 enable bit */
		io_byte ADTRGD1E:1;		/* A/D trigger D1 enable bit */
	} BIT;
} TRDADCR;
#define		TRDADCR		(*(volatile union TRDADCR_T *) 0x0136)

/*------------------------------------------------------------------------------------
  Timer RD Start Register
------------------------------------------------------------------------------------*/
typedef union TRDSTR_T
{
	io_byte REG;
	struct
	{
		io_byte TSTART0:1;		/* TRD0 count start flag */
		io_byte TSTART1:1;		/* TRD1 count start flag */
		io_byte CSEL0:1;		/* TRD0 count operation select bit */
		io_byte CSEL1:1;		/* TRD1 count operation select bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRDSTR;
#define		TRDSTR		(*(volatile union TRDSTR_T *) 0x0137)

/*------------------------------------------------------------------------------------
  Timer RD Mode Register
------------------------------------------------------------------------------------*/
typedef union TRDMR_T
{
	io_byte REG;
	struct
	{
		io_byte SYNC:1;		/* Timer RD synchronous bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte BFC0:1;		/* TRDGRC0 register function select bit */
		io_byte BFD0:1;		/* TRDGRD0 register function select bit */
		io_byte BFC1:1;		/* TRDGRC1 register function select bit */
		io_byte BFD1:1;		/* TRDGRD1 register function select bit */
	} BIT;
} TRDMR;
#define		TRDMR		(*(volatile union TRDMR_T *) 0x0138)

/*------------------------------------------------------------------------------------
  Timer RD PWM Mode Register
------------------------------------------------------------------------------------*/
typedef union TRDPMR_T
{
	io_byte REG;
	struct
	{
		io_byte PWMB0:1;		/* PWM mode of TRDIOB0 select bit */
		io_byte PWMC0:1;		/* PWM mode of TRDIOC0 select bit */
		io_byte PWMD0:1;		/* PWM mode of TRDIOD0 select bit */
		io_byte B3:1;
		io_byte PWMB1:1;		/* PWM mode of TRDIOB1 select bit */
		io_byte PWMC1:1;		/* PWM mode of TRDIOC1 select bit */
		io_byte PWMD1:1;		/* PWM mode of TRDIOD1 select bit */
		io_byte B7:1;
	} BIT;
} TRDPMR;
#define		TRDPMR		(*(volatile union TRDPMR_T *) 0x0139)

/*------------------------------------------------------------------------------------
  Timer RD Function Control Register
------------------------------------------------------------------------------------*/
typedef union TRDFCR_T
{
	io_byte REG;
	struct
	{
		io_byte CMD0:1;		/* Combination mode select bit */
		io_byte CMD1:1;		/* Combination mode select bit */
		io_byte OLS0:1;		/* Normal-Phase output level select bit */
		io_byte OLS1:1;		/* Counter-Phase output level select bit */
		io_byte ADTRG:1;		/* A/D trigger enable bit */
		io_byte ADEG:1;		/* A/D trigger edge select bit */
		io_byte STCLK:1;		/* External clock input select bit */
		io_byte PWM3:1;		/* PWM3 mode select bit */
	} BIT;
} TRDFCR;
#define		TRDFCR		(*(volatile union TRDFCR_T *) 0x013A)

/*------------------------------------------------------------------------------------
  Timer RD Output Master Enable Register 1
------------------------------------------------------------------------------------*/
typedef union TRDOER1_T
{
	io_byte REG;
	struct
	{
		io_byte EA0:1;		/* TRDIOA0 output disable bit */
		io_byte EB0:1;		/* TRDIOB0 output disable bit */
		io_byte EC0:1;		/* TRDIOC0 output disable bit */
		io_byte ED0:1;		/* TRDIOD0 output disable bit */
		io_byte EA1:1;		/* TRDIOA1 output disable bit */
		io_byte EB1:1;		/* TRDIOB1 output disable bit */
		io_byte EC1:1;		/* TRDIOC1 output disable bit */
		io_byte ED1:1;		/* TRDIOD1 output disable bit */
	} BIT;
} TRDOER1;
#define		TRDOER1		(*(volatile union TRDOER1_T *) 0x013B)

/*------------------------------------------------------------------------------------
  Timer RD Output Master Enable Register 2
------------------------------------------------------------------------------------*/
typedef union TRDOER2_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte PTO:1;		/* INT0 of pulse output forced cutoff signal input enabled bit */
	} BIT;
} TRDOER2;
#define		TRDOER2		(*(volatile union TRDOER2_T *) 0x013C)

/*------------------------------------------------------------------------------------
  Timer RD Output Control Register
------------------------------------------------------------------------------------*/
typedef union TRDOCR_T
{
	io_byte REG;
	struct
	{
		io_byte TOA0:1;		/* TRDIOA0 output level select bit */
		io_byte TOB0:1;		/* TRDIOB0 output level select bit */
		io_byte TOC0:1;		/* TRDIOC0 initial output level select bit */
		io_byte TOD0:1;		/* TRDIOD0 initial output level select bit */
		io_byte TOA1:1;		/* TRDIOA1 initial output level select bit */
		io_byte TOB1:1;		/* TRDIOB1 initial output level select bit */
		io_byte TOC1:1;		/* TRDIOC1 initial output level select bit */
		io_byte TOD1:1;		/* TRDIOD1 initial output level select bit */
	} BIT;
} TRDOCR;
#define		TRDOCR		(*(volatile union TRDOCR_T *) 0x013D)

/*------------------------------------------------------------------------------------
  Timer RD Digital Filter Function Select Register 0
------------------------------------------------------------------------------------*/
typedef union TRDDF0_T
{
	io_byte REG;
	struct
	{
		io_byte DFA:1;		/* TRDIOA pin digital filter function select bit */
		io_byte DFB:1;		/* TRDIOB pin digital filter function select bit */
		io_byte DFC:1;		/* TRDIOC pin digital filter function select bit */
		io_byte DFD:1;		/* TRDIOD pin digital filter function select bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte DFCK0:1;		/* Clock select bits for digital filter function */
		io_byte DFCK1:1;		/* Clock select bits for digital filter function */
	} BIT;
} TRDDF0;
#define		TRDDF0		(*(volatile union TRDDF0_T *) 0x013E)

/*------------------------------------------------------------------------------------
  Timer RD Digital Filter Function Select Register 1
------------------------------------------------------------------------------------*/
typedef union TRDDF1_T
{
	io_byte REG;
	struct
	{
		io_byte DFA:1;		/* TRDIOA pin digital filter function select bit */
		io_byte DFB:1;		/* TRDIOB pin digital filter function select bit */
		io_byte DFC:1;		/* TRDIOC pin digital filter function select bit */
		io_byte DFD:1;		/* TRDIOD pin digital filter function select bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte DFCK0:1;		/* Clock select bits for digital filter function */
		io_byte DFCK1:1;		/* Clock select bits for digital filter function */
	} BIT;
} TRDDF1;
#define		TRDDF1		(*(volatile union TRDDF1_T *) 0x013F)

/*------------------------------------------------------------------------------------
  Timer RD Control Register 0
------------------------------------------------------------------------------------*/
typedef union TRDCR0_T
{
	io_byte REG;
	struct
	{
		io_byte TCK0:1;		/* Count source select bit */
		io_byte TCK1:1;		/* Count source select bit */
		io_byte TCK2:1;		/* Count source select bit */
		io_byte CKEG0:1;		/* External clock edge select bit */
		io_byte CKEG1:1;		/* External clock edge select bit */
		io_byte CCLR0:1;		/* TRD0 counter clear select bit */
		io_byte CCLR1:1;		/* TRD0 counter clear select bit */
		io_byte CCLR2:1;		/* TRD0 counter clear select bit */
	} BIT;
} TRDCR0;
#define		TRDCR0		(*(volatile union TRDCR0_T *) 0x0140)

/*------------------------------------------------------------------------------------
  Timer RD I/O Control Register A0
------------------------------------------------------------------------------------*/
typedef union TRDIORA0_T
{
	io_byte REG;
	struct
	{
		io_byte IOA0:1;		/* TRDGRA control bit */
		io_byte IOA1:1;		/* TRDGRA control bit */
		io_byte IOA2:1;		/* TRDGRA mode select bit */
		io_byte IOA3:1;		/* Input capture input switch bit */
		io_byte IOB0:1;		/* TRDGRB control bit */
		io_byte IOB1:1;		/* TRDGRB control bit */
		io_byte IOB2:1;		/* TRDGRB mode select bit */
		io_byte B7:1;
	} BIT;
} TRDIORA0;
#define		TRDIORA0		(*(volatile union TRDIORA0_T *) 0x0141)

/*------------------------------------------------------------------------------------
  Timer RD I/O Control Register C0
------------------------------------------------------------------------------------*/
typedef union TRDIORC0_T
{
	io_byte REG;
	struct
	{
		io_byte IOC0:1;		/* TRDGRC control bit */
		io_byte IOC1:1;		/* TRDGRC control bit */
		io_byte IOC2:1;		/* TRDGRC mode select bit */
		io_byte IOC3:1;		/* TRDGRC register function select bit */
		io_byte IOD0:1;		/* TRDGRD control bit */
		io_byte IOD1:1;		/* TRDGRD control bit */
		io_byte IOD2:1;		/* TRDGRD mode select bit */
		io_byte IOD3:1;		/* TRDGRD register function select bit */
	} BIT;
} TRDIORC0;
#define		TRDIORC0		(*(volatile union TRDIORC0_T *) 0x0142)

/*------------------------------------------------------------------------------------
  Timer RD Status Register 0
------------------------------------------------------------------------------------*/
typedef union TRDSR0_T
{
	io_byte REG;
	struct
	{
		io_byte IMFA:1;		/* Input capture / compare match flag A */
		io_byte IMFB:1;		/* Input capture / compare match flag B */
		io_byte IMFC:1;		/* Input capture / compare match flag C */
		io_byte IMFD:1;		/* Input capture / compare match flag D */
		io_byte OVF:1;		/* Overflow flag */
		io_byte UDF:1;		/* Underflow flag */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRDSR0;
#define		TRDSR0		(*(volatile union TRDSR0_T *) 0x0143)

/*------------------------------------------------------------------------------------
  Timer RD Interrupt Enable Register 0
------------------------------------------------------------------------------------*/
typedef union TRDIER0_T
{
	io_byte REG;
	struct
	{
		io_byte IMIEA:1;		/* Input capture / compare match interrupt enable bit A */
		io_byte IMIEB:1;		/* Input capture / compare match interrupt enable bit B */
		io_byte IMIEC:1;		/* Input capture / compare match interrupt enable bit C */
		io_byte IMIED:1;		/* Input capture / compare match interrupt enable bit D */
		io_byte OVIE:1;		/* Overflow / underflow interrupt enable bit */
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRDIER0;
#define		TRDIER0		(*(volatile union TRDIER0_T *) 0x0144)

/*------------------------------------------------------------------------------------
  Timer RD PWM Mode Output Level Control Register 0
------------------------------------------------------------------------------------*/
typedef union TRDPOCR0_T
{
	io_byte REG;
	struct
	{
		io_byte POLB:1;		/* PWM mode output level control bit B */
		io_byte POLC:1;		/* PWM mode output level control bit C */
		io_byte POLD:1;		/* PWM mode output level control bit D */
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRDPOCR0;
#define		TRDPOCR0		(*(volatile union TRDPOCR0_T *) 0x0145)

/*------------------------------------------------------------------------------------
  Timer RD Control Register 1
------------------------------------------------------------------------------------*/
typedef union TRDCR1_T
{
	io_byte REG;
	struct
	{
		io_byte TCK0:1;		/* Count source select bit */
		io_byte TCK1:1;		/* Count source select bit */
		io_byte TCK2:1;		/* Count source select bit */
		io_byte CKEG0:1;		/* External clock edge select bit */
		io_byte CKEG1:1;		/* External clock edge select bit */
		io_byte CCLR0:1;		/* TRD1 counter clear select bit */
		io_byte CCLR1:1;		/* TRD1 counter clear select bit */
		io_byte CCLR2:1;		/* TRD1 counter clear select bit */
	} BIT;
} TRDCR1;
#define		TRDCR1		(*(volatile union TRDCR1_T *) 0x0150)

/*------------------------------------------------------------------------------------
  Timer RD I/O Control Register A1
------------------------------------------------------------------------------------*/
typedef union TRDIORA1_T
{
	io_byte REG;
	struct
	{
		io_byte IOA0:1;		/* TRDGRA control bit */
		io_byte IOA1:1;		/* TRDGRA control bit */
		io_byte IOA2:1;		/* TRDGRA mode select bit */
		io_byte IOA3:1;		/* Input capture input switch bit */
		io_byte IOB0:1;		/* TRDGRB control bit */
		io_byte IOB1:1;		/* TRDGRB control bit */
		io_byte IOB2:1;		/* TRDGRB mode select bit */
		io_byte B7:1;
	} BIT;
} TRDIORA1;
#define		TRDIORA1		(*(volatile union TRDIORA1_T *) 0x0151)

/*------------------------------------------------------------------------------------
  Timer RD I/O Control Register C1
------------------------------------------------------------------------------------*/
typedef union TRDIORC1_T
{
	io_byte REG;
	struct
	{
		io_byte IOC0:1;		/* TRDGRC control bit */
		io_byte IOC1:1;		/* TRDGRC control bit */
		io_byte IOC2:1;		/* TRDGRC mode select bit */
		io_byte IOC3:1;		/* TRDGRC register function select bit */
		io_byte IOD0:1;		/* TRDGRD control bit */
		io_byte IOD1:1;		/* TRDGRD control bit */
		io_byte IOD2:1;		/* TRDGRD mode select bit */
		io_byte IOD3:1;		/* TRDGRD register function select bit */
	} BIT;
} TRDIORC1;
#define		TRDIORC1		(*(volatile union TRDIORC1_T *) 0x0152)

/*------------------------------------------------------------------------------------
  Timer RD Status Register 1
------------------------------------------------------------------------------------*/
typedef union TRDSR1_T
{
	io_byte REG;
	struct
	{
		io_byte IMFA:1;		/* Input capture / compare match flag A */
		io_byte IMFB:1;		/* Input capture / compare match flag B */
		io_byte IMFC:1;		/* Input capture / compare match flag C */
		io_byte IMFD:1;		/* Input capture / compare match flag D */
		io_byte OVF:1;		/* Overflow flag */
		io_byte UDF:1;		/* Underflow flag */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRDSR1;
#define		TRDSR1		(*(volatile union TRDSR1_T *) 0x0153)

/*------------------------------------------------------------------------------------
  Timer RD Interrupt Enable Register 1
------------------------------------------------------------------------------------*/
typedef union TRDIER1_T
{
	io_byte REG;
	struct
	{
		io_byte IMIEA:1;		/* Input capture / compare match interrupt enable bit A */
		io_byte IMIEB:1;		/* Input capture / compare match interrupt enable bit B */
		io_byte IMIEC:1;		/* Input capture / compare match interrupt enable bit C */
		io_byte IMIED:1;		/* Input capture / compare match interrupt enable bit D */
		io_byte OVIE:1;		/* Overflow / underflow interrupt enable bit */
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRDIER1;
#define		TRDIER1		(*(volatile union TRDIER1_T *) 0x0154)

/*------------------------------------------------------------------------------------
  Timer RD PWM Mode Output Level Control Register 1
------------------------------------------------------------------------------------*/
typedef union TRDPOCR1_T
{
	io_byte REG;
	struct
	{
		io_byte POLB:1;		/* PWM mode output level control bit B */
		io_byte POLC:1;		/* PWM mode output level control bit C */
		io_byte POLD:1;		/* PWM mode output level control bit D */
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRDPOCR1;
#define		TRDPOCR1		(*(volatile union TRDPOCR1_T *) 0x0155)

/*------------------------------------------------------------------------------------
  UART1 Bit Rate Register
------------------------------------------------------------------------------------*/
typedef union U1BRG_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} U1BRG;
#define		U1BRG		(*(volatile union U1BRG_T *) 0x0161)

/*------------------------------------------------------------------------------------
  Timer RG Mode Register
------------------------------------------------------------------------------------*/
typedef union TRGMR_T
{
	io_byte REG;
	struct
	{
		io_byte PWM:1;		/* PWM mode select bit */
		io_byte MDF:1;		/* Phase counting mode select bit */
		io_byte DFA:1;		/* Digital filer function select bit for TRGIOA pin */
		io_byte DFB:1;		/* Digital filer function select bit for TRGIOB pin */
		io_byte DFCK0:1;		/* Digital filter function clock select bit */
		io_byte DFCK1:1;		/* Digital filter function clock select bit */
		io_byte B6:1;
		io_byte TSTART:1;		/* TRG count start bit */
	} BIT;
} TRGMR;
#define		TRGMR		(*(volatile union TRGMR_T *) 0x0170)

/*------------------------------------------------------------------------------------
  Timer RG Counter Control Register
------------------------------------------------------------------------------------*/
typedef union TRGCNTC_T
{
	io_byte REG;
	struct
	{
		io_byte CNTEN0:1;		/* Counter enable bit 0 */
		io_byte CNTEN1:1;		/* Counter enable bit 1 */
		io_byte CNTEN2:1;		/* Counter enable bit 2 */
		io_byte CNTEN3:1;		/* Counter enable bit 3 */
		io_byte CNTEN4:1;		/* Counter enable bit 4 */
		io_byte CNTEN5:1;		/* Counter enable bit 5 */
		io_byte CNTEN6:1;		/* Counter enable bit 6 */
		io_byte CNTEN7:1;		/* Counter enable bit 7 */
	} BIT;
} TRGCNTC;
#define		TRGCNTC		(*(volatile union TRGCNTC_T *) 0x0171)

/*------------------------------------------------------------------------------------
  Timer RG Control Register
------------------------------------------------------------------------------------*/
typedef union TRGCR_T
{
	io_byte REG;
	struct
	{
		io_byte TCK0:1;		/* Count source select bit */
		io_byte TCK1:1;		/* Count source select bit */
		io_byte TCK2:1;		/* Count source select bit */
		io_byte CKEG0:1;		/* External clock active edge select bit */
		io_byte CKEG1:1;		/* External clock active edge select bit */
		io_byte CCLR0:1;		/* TRG register clear source select bit */
		io_byte CCLR1:1;		/* TRG register clear source select bit */
		io_byte B7:1;
	} BIT;
} TRGCR;
#define		TRGCR		(*(volatile union TRGCR_T *) 0x0172)

/*------------------------------------------------------------------------------------
  Timer RG Interrupt Enable Register
------------------------------------------------------------------------------------*/
typedef union TRGIER_T
{
	io_byte REG;
	struct
	{
		io_byte IMIEA:1;		/* Input-capture/compare-match interrupt enable bit A */
		io_byte IMIEB:1;		/* Input-capture/compare-match interrupt enable bit B */
		io_byte UDIE:1;		/* Underflow interrupt enable bit */
		io_byte OVIE:1;		/* Overflow interrupt enable bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRGIER;
#define		TRGIER		(*(volatile union TRGIER_T *) 0x0173)

/*------------------------------------------------------------------------------------
  Timer RG Status Register
------------------------------------------------------------------------------------*/
typedef union TRGSR_T
{
	io_byte REG;
	struct
	{
		io_byte IMFA:1;		/* Input-capture/compare-match flag A */
		io_byte IMFB:1;		/* Input-capture/compare-match flag B */
		io_byte UDF:1;		/* Underflow flag */
		io_byte OVF:1;		/* Overflow flag */
		io_byte DIRF:1;		/* Count direction flag */
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRGSR;
#define		TRGSR		(*(volatile union TRGSR_T *) 0x0174)

/*------------------------------------------------------------------------------------
  Timer RG I/O Control Register
------------------------------------------------------------------------------------*/
typedef union TRGIOR_T
{
	io_byte REG;
	struct
	{
		io_byte IOA0:1;		/* TRGGRA control bit */
		io_byte IOA1:1;		/* TRGGRA control bit */
		io_byte IOA2:1;		/* TRGGRA mode select bit */
		io_byte BUFA:1;		/* TRGGRC register function select bit */
		io_byte IOB0:1;		/* TRGGRB control bit */
		io_byte IOB1:1;		/* TRGGRB control bit */
		io_byte IOB2:1;		/* TRGGRB mode select bit */
		io_byte BUFB:1;		/* TRGGRD register function select bit */
	} BIT;
} TRGIOR;
#define		TRGIOR		(*(volatile union TRGIOR_T *) 0x0175)

/*------------------------------------------------------------------------------------
  Timer RG Counter, Timer RG General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRG_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRG;
#define		TRG		(*(volatile union TRG_T *) 0x0176)

/*------------------------------------------------------------------------------------
  Timer RG Counter, Timer RG General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRGGRA_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRGGRA;
#define		TRGGRA		(*(volatile union TRGGRA_T *) 0x0178)

/*------------------------------------------------------------------------------------
  Timer RG Counter, Timer RG General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRGGRB_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRGGRB;
#define		TRGGRB		(*(volatile union TRGGRB_T *) 0x017A)

/*------------------------------------------------------------------------------------
  Timer RG Counter, Timer RG General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRGGRC_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRGGRC;
#define		TRGGRC		(*(volatile union TRGGRC_T *) 0x017C)

/*------------------------------------------------------------------------------------
  Timer RG Counter, Timer RG General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRGGRD_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRGGRD;
#define		TRGGRD		(*(volatile union TRGGRD_T *) 0x017E)

/*------------------------------------------------------------------------------------
  Timer RA Pin Select Register
------------------------------------------------------------------------------------*/
typedef union TRASR_T
{
	io_byte REG;
	struct
	{
		io_byte TRAIOSEL0:1;		/* TRAIO0 pin select bit */
		io_byte TRAIOSEL1:1;		/* TRAIO0 pin select bit */
		io_byte B2:1;
		io_byte TRAOSEL0:1;		/* TRAO0 pin select bit */
		io_byte B4:1;
		io_byte TRAIO1SEL0:1;		/* TRAIO1 pin select bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} TRASR;
#define		TRASR		(*(volatile union TRASR_T *) 0x0180)

/*------------------------------------------------------------------------------------
  Timer RB/RC Pin Select Register
------------------------------------------------------------------------------------*/
typedef union TRBRCSR_T
{
	io_byte REG;
	struct
	{
		io_byte TRBOSEL0:1;		/* TRBO pin select bit */
		io_byte TRBOSEL1:1;		/* TRBO pin select bit */
		io_byte B2:1;
		io_byte B3:1;
		io_byte TRCCLKSEL0:1;		/* TRCCLK pin select bit */
		io_byte TRCCLKSEL1:1;		/* TRCCLK pin select bit */
		io_byte TRCCLKSEL2:1;		/* TRCCLK pin select bit */
		io_byte B7:1;
	} BIT;
} TRBRCSR;
#define		TRBRCSR		(*(volatile union TRBRCSR_T *) 0x0181)

/*------------------------------------------------------------------------------------
  Timer RC Pin Select Register 0
------------------------------------------------------------------------------------*/
typedef union TRCPSR0_T
{
	io_byte REG;
	struct
	{
		io_byte TRCIOASEL0:1;		/* TRCIOA/TRCTRG pin select bit */
		io_byte TRCIOASEL1:1;		/* TRCIOA/TRCTRG pin select bit */
		io_byte TRCIOASEL2:1;		/* TRCIOA/TRCTRG pin select bit */
		io_byte B3:1;
		io_byte TRCIOBSEL0:1;		/* TRCIOB pin select bit */
		io_byte TRCIOBSEL1:1;		/* TRCIOB pin select bit */
		io_byte TRCIOBSEL2:1;		/* TRCIOB pin select bit */
		io_byte B7:1;
	} BIT;
} TRCPSR0;
#define		TRCPSR0		(*(volatile union TRCPSR0_T *) 0x0182)

/*------------------------------------------------------------------------------------
  Timer RC Pin Select Register 1
------------------------------------------------------------------------------------*/
typedef union TRCPSR1_T
{
	io_byte REG;
	struct
	{
		io_byte TRCIOCSEL0:1;		/* TRCIOC pin select bit */
		io_byte TRCIOCSEL1:1;		/* TRCIOC pin select bit */
		io_byte TRCIOCSEL2:1;		/* TRCIOC pin select bit */
		io_byte B3:1;
		io_byte TRCIODSEL0:1;		/* TRCIOD pin select bit */
		io_byte TRCIODSEL1:1;		/* TRCIOD pin select bit */
		io_byte TRCIODSEL2:1;		/* TRCIOD pin select bit */
		io_byte B7:1;
	} BIT;
} TRCPSR1;
#define		TRCPSR1		(*(volatile union TRCPSR1_T *) 0x0183)

/*------------------------------------------------------------------------------------
  Timer RD Pin Select Register 0
------------------------------------------------------------------------------------*/
typedef union TRDPSR0_T
{
	io_byte REG;
	struct
	{
		io_byte TRDIOA0SEL0:1;		/* TRDIOA0/TRDCLK pin select bit */
		io_byte B1:1;
		io_byte TRDIOB0SEL0:1;		/* TRDIOB0 pin select bit */
		io_byte B3:1;
		io_byte TRDIOC0SEL0:1;		/* TRDIOC0 pin select bit */
		io_byte B5:1;
		io_byte TRDIOD0SEL0:1;		/* TRDIOD0 pin select bit */
		io_byte B7:1;
	} BIT;
} TRDPSR0;
#define		TRDPSR0		(*(volatile union TRDPSR0_T *) 0x0184)

/*------------------------------------------------------------------------------------
  Timer RD Pin Select Register 1
------------------------------------------------------------------------------------*/
typedef union TRDPSR1_T
{
	io_byte REG;
	struct
	{
		io_byte TRDIOA1SEL0:1;		/* TRDIOA1 pin select bit */
		io_byte B1:1;
		io_byte TRDIOB1SEL0:1;		/* TRDIOB1 pin select bit */
		io_byte B3:1;
		io_byte TRDIOC1SEL0:1;		/* TRDIOC1 pin select bit */
		io_byte B5:1;
		io_byte TRDIOD1SEL0:1;		/* TRDIOD1 pin select bit */
		io_byte B7:1;
	} BIT;
} TRDPSR1;
#define		TRDPSR1		(*(volatile union TRDPSR1_T *) 0x0185)

/*------------------------------------------------------------------------------------
  Timer Pin Select Register
------------------------------------------------------------------------------------*/
typedef union TIMSR_T
{
	io_byte REG;
	struct
	{
		io_byte TREOSEL0:1;		/* TREO pin select bit */
		io_byte B1:1;
		io_byte TRFISEL0:1;		/* TRFI pin select bit */
		io_byte B3:1;
		io_byte TRGIOASEL:1;		/* TRGIOA pin select bit */
		io_byte TRGIOBSEL:1;		/* TRGIOB pin select bit */
		io_byte TRGCLKASEL:1;		/* TRGCLKA pin select bit */
		io_byte TRGCLKBSEL:1;		/* TRGCLKB pin select bit */
	} BIT;
} TIMSR;
#define		TIMSR		(*(volatile union TIMSR_T *) 0x0186)

/*------------------------------------------------------------------------------------
  Timer RF Output Control Register
------------------------------------------------------------------------------------*/
typedef union TRFOUT_T
{
	io_byte REG;
	struct
	{
		io_byte TRFOUT0:1;		/* TRFO00 output enable bit 0 */
		io_byte TRFOUT1:1;		/* TRFO01 output enable bit 1 */
		io_byte TRFOUT2:1;		/* TRFO02 output enable bit 2 */
		io_byte TRFOUT3:1;		/* TRFO10 output enable bit 3 */
		io_byte TRFOUT4:1;		/* TRFO11 output enable bit 4 */
		io_byte TRFOUT5:1;		/* TRFO12 output enable bit 5 */
		io_byte TRFOUT6:1;		/* TRFO00 to TRFO02 output reverse bit */
		io_byte TRFOUT7:1;		/* TRFO10 to TRFO12 output reverse bit */
	} BIT;
} TRFOUT;
#define		TRFOUT		(*(volatile union TRFOUT_T *) 0x0187)

/*------------------------------------------------------------------------------------
  UART0 Pin Select Register
------------------------------------------------------------------------------------*/
typedef union U0SR_T
{
	io_byte REG;
	struct
	{
		io_byte TXD0SEL0:1;		/* TXD0 pin select bit */
		io_byte B1:1;
		io_byte RXD0SEL0:1;		/* RXD0 pin select bit */
		io_byte B3:1;
		io_byte CLK0SEL0:1;		/* CLK0 pin select bit */
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} U0SR;
#define		U0SR		(*(volatile union U0SR_T *) 0x0188)

/*------------------------------------------------------------------------------------
  UART1 Pin Select Register
------------------------------------------------------------------------------------*/
typedef union U1SR_T
{
	io_byte REG;
	struct
	{
		io_byte TXD1SEL0:1;		/* TXD1 pin select bit */
		io_byte TXD1SEL1:1;		/* TXD1 pin select bit */
		io_byte RXD1SEL0:1;		/* RXD1 pin select bit */
		io_byte RXD1SEL1:1;		/* RXD1 pin select bit */
		io_byte CLK1SEL0:1;		/* CLK1 pin select bit */
		io_byte CLK1SEL1:1;		/* CLK1 pin select bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} U1SR;
#define		U1SR		(*(volatile union U1SR_T *) 0x0189)

/*------------------------------------------------------------------------------------
  UART2 Pin Select Register 0
------------------------------------------------------------------------------------*/
typedef union U2SR0_T
{
	io_byte REG;
	struct
	{
		io_byte TXD2SEL0:1;		/* TXD2/SDA2 pin select bit */
		io_byte TXD2SEL1:1;		/* TXD2/SDA2 pin select bit */
		io_byte TXD2SEL2:1;		/* TXD2/SDA2 pin select bit */
		io_byte B3:1;
		io_byte RXD2SEL0:1;		/* RXD2/SCL2 pin select bit */
		io_byte RXD2SEL1:1;		/* RXD2/SCL2 pin select bit */
		io_byte RXD2SEL2:1;		/* RXD2/SCL2 pin select bit */
		io_byte B7:1;
	} BIT;
} U2SR0;
#define		U2SR0		(*(volatile union U2SR0_T *) 0x018A)

/*------------------------------------------------------------------------------------
  UART2 Pin Select Register 1
------------------------------------------------------------------------------------*/
typedef union U2SR1_T
{
	io_byte REG;
	struct
	{
		io_byte CLK2SEL0:1;		/* CLK2 pin select bit */
		io_byte CLK2SEL1:1;		/* CLK2 pin select bit */
		io_byte B2:1;
		io_byte B3:1;
		io_byte CTS2SEL0:1;		/* CTS2/RTS2 pin select bit */
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} U2SR1;
#define		U2SR1		(*(volatile union U2SR1_T *) 0x018B)

/*------------------------------------------------------------------------------------
  SSU Pin Select Register
------------------------------------------------------------------------------------*/
typedef union SSUIICSR_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte SSISEL0:1;		/* SSI pin select bit */
		io_byte B5:1;
		io_byte SCSSEL0:1;		/* SCS pin select bit */
		io_byte B7:1;
	} BIT;
} SSUIICSR;
#define		SSUIICSR		(*(volatile union SSUIICSR_T *) 0x018C)

/*------------------------------------------------------------------------------------
  INT Interrupt Input Pin Select Register
------------------------------------------------------------------------------------*/
typedef union INTSR_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte INT1SEL0:1;		/* INT1 pin select bit */
		io_byte INT1SEL1:1;		/* INT1 pin select bit */
		io_byte INT1SEL2:1;		/* INT1 pin select bit */
		io_byte INT2SEL0:1;		/* INT2 pin select bit */
		io_byte INT2SEL1:1;		/* INT2 pin select bit */
		io_byte INT3SEL0:1;		/* INT3 pin select bit */
		io_byte INT3SEL1:1;		/* INT3 pin select bit */
	} BIT;
} INTSR;
#define		INTSR		(*(volatile union INTSR_T *) 0x018E)

/*------------------------------------------------------------------------------------
  I/O Function Pin Select Register
------------------------------------------------------------------------------------*/
typedef union PINSR_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte IOINSEL:1;		/* I/O port input function select bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} PINSR;
#define		PINSR		(*(volatile union PINSR_T *) 0x018F)

/*------------------------------------------------------------------------------------
  SS Bit Counter Register
------------------------------------------------------------------------------------*/
typedef union SSBR_T
{
	io_byte REG;
	struct
	{
		io_byte BS0:1;		/* SSU data transfer length set bit */
		io_byte BS1:1;		/* SSU data transfer length set bit */
		io_byte BS2:1;		/* SSU data transfer length set bit */
		io_byte BS3:1;		/* SSU data transfer length set bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} SSBR;
#define		SSBR		(*(volatile union SSBR_T *) 0x0193)

/*------------------------------------------------------------------------------------
  SS Control Register H
------------------------------------------------------------------------------------*/
typedef union SSCRH_T
{
	io_byte REG;
	struct
	{
		io_byte CKS0:1;		/* Transfer clock select bit */
		io_byte CKS1:1;		/* Transfer clock select bit */
		io_byte CKS2:1;		/* Transfer clock select bit */
		io_byte B3:1;
		io_byte B4:1;
		io_byte MSS:1;		/* Master/Slave device select bit */
		io_byte RSSTP:1;		/* Receive single stop bit */
		io_byte B7:1;
	} BIT;
} SSCRH;
#define		SSCRH		(*(volatile union SSCRH_T *) 0x0198)

/*------------------------------------------------------------------------------------
  SS Control Register L
------------------------------------------------------------------------------------*/
typedef union SSCRL_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte SRES:1;		/* SSU control unit reset bit */
		io_byte B2:1;
		io_byte B3:1;
		io_byte SOLP:1;		/* SOL write protect bit */
		io_byte SOL:1;		/* Serial data output value setting bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} SSCRL;
#define		SSCRL		(*(volatile union SSCRL_T *) 0x0199)

/*------------------------------------------------------------------------------------
  SS Mode Register
------------------------------------------------------------------------------------*/
typedef union SSMR_T
{
	io_byte REG;
	struct
	{
		io_byte BC0:1;		/* Bit counter 3 to 0 */
		io_byte BC1:1;		/* Bit counter 3 to 0 */
		io_byte BC2:1;		/* Bit counter 3 to 0 */
		io_byte BC3:1;		/* Bit counter 3 to 0 */
		io_byte B4:1;
		io_byte CPHS:1;		/* SSCK clock phase select bit */
		io_byte CPOS:1;		/* SSCK clock polarity select bit */
		io_byte MLS:1;		/* MSB first/ LSB first select bit */
	} BIT;
} SSMR;
#define		SSMR		(*(volatile union SSMR_T *) 0x019A)

/*------------------------------------------------------------------------------------
  SS Enable Register 
------------------------------------------------------------------------------------*/
typedef union SSER_T
{
	io_byte REG;
	struct
	{
		io_byte CEIE:1;		/* Conflict error interrupt enable bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte RE:1;		/* Receive enable bit */
		io_byte TE:1;		/* Transmit enable bit */
		io_byte RIE:1;		/* Receive interrupt enable bit */
		io_byte TEIE:1;		/* Transmit end interrupt enable bit */
		io_byte TIE:1;		/* Transmit interrupt enable bit */
	} BIT;
} SSER;
#define		SSER		(*(volatile union SSER_T *) 0x019B)

/*------------------------------------------------------------------------------------
  SS Status Register
------------------------------------------------------------------------------------*/
typedef union SSSR_T
{
	io_byte REG;
	struct
	{
		io_byte CE:1;		/* Conflict error flag */
		io_byte B1:1;
		io_byte ORER:1;		/* Overrun error flag */
		io_byte B3:1;
		io_byte B4:1;
		io_byte RDRF:1;		/* Receive data Register full flag */
		io_byte TEND:1;		/* Transmit end flag */
		io_byte TDRE:1;		/* Transmit data empty flag */
	} BIT;
} SSSR;
#define		SSSR		(*(volatile union SSSR_T *) 0x019C)

/*------------------------------------------------------------------------------------
  SS Mode Register 2
------------------------------------------------------------------------------------*/
typedef union SSMR2_T
{
	io_byte REG;
	struct
	{
		io_byte SSUMS:1;		/* SSU mode select bit */
		io_byte CSOS:1;		/* SCS pin open-drain output select bit */
		io_byte SOOS:1;		/* Serial data open-drain output select bit */
		io_byte SCKOS:1;		/* SSCK pin open-drain output select bit */
		io_byte CSS0:1;		/* SCS pin selsct bit */
		io_byte CSS1:1;		/* SCS pin select bit */
		io_byte SCKS:1;		/* SSCK pin select bit */
		io_byte BIDE:1;		/* Bidirectional mode enable bit */
	} BIT;
} SSMR2;
#define		SSMR2		(*(volatile union SSMR2_T *) 0x019D)

/*------------------------------------------------------------------------------------
  Flash Memory Status Register
------------------------------------------------------------------------------------*/
typedef union FST_T
{
	io_byte REG;
	struct
	{
		io_byte RDYSTI:1;		/* Flash ready status interrupt request flag */
		io_byte BSYAEI:1;		/* Flash access error interrupt request flag */
		io_byte LBDATA:1;		/* LBDATA monitor flag */
		io_byte B3:1;
		io_byte FST4:1;		/* Program error flag */
		io_byte FST5:1;		/* Erase error/blank check error flag */
		io_byte FST6:1;		/* Erase suspend status flag */
		io_byte FST7:1;		/* Ready/Busy status flag */
	} BIT;
} FST;
#define		FST		(*(volatile union FST_T *) 0x01B2)

/*------------------------------------------------------------------------------------
  Flash Memory Control Register 0
------------------------------------------------------------------------------------*/
typedef union FMR0_T
{
	io_byte REG;
	struct
	{
		io_byte FMR00:1;		/* Program unit select bit */
		io_byte FMR01:1;		/* CPU rewrite mode select bit */
		io_byte FMR02:1;		/* EW1 mode select bit */
		io_byte FMSTP:1;		/* Flash memory stop bit */
		io_byte CMDRST:1;		/* Erase/Write sequence reset bit */
		io_byte CMDERIE:1;		/* Erase/Write error interrupt enable bit */
		io_byte BSYAEIE:1;		/* Flash access error interrupt enable bit */
		io_byte RDYSTIE:1;		/* Flash ready status interrupt enable bit */
	} BIT;
} FMR0;
#define		FMR0		(*(volatile union FMR0_T *) 0x01B4)

/*------------------------------------------------------------------------------------
  Flash Memory Control Register 1
------------------------------------------------------------------------------------*/
typedef union FMR1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte FMR13:1;		/* Lock bit disable select bit */
		io_byte FMR14:1;		/* Data flash block A rewrite disable bit */
		io_byte FMR15:1;		/* Data flash block B rewrite disable bit */
		io_byte FMR16:1;		/* Data flash block C rewrite disable bit */
		io_byte FMR17:1;		/* Data flash block D rewrite disable bit */
	} BIT;
} FMR1;
#define		FMR1		(*(volatile union FMR1_T *) 0x01B5)

/*------------------------------------------------------------------------------------
  Flash Memory Control Register 1
------------------------------------------------------------------------------------*/
typedef union FMR2_T
{
	io_byte REG;
	struct
	{
		io_byte FMR20:1;		/* Erase suspend enable bit */
		io_byte FMR21:1;		/* Erase suspend request bit */
		io_byte FMR22:1;		/* Interrupt request suspend request enable bit */
		io_byte FMR23:1;		/* Data flash access cycle select bit */
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte FMR27:1;		/* Low-consumption-current read mode enable bit */
	} BIT;
} FMR2;
#define		FMR2		(*(volatile union FMR2_T *) 0x01B6)

/*------------------------------------------------------------------------------------
  Address Match Interrupt Enable Register 0
------------------------------------------------------------------------------------*/
typedef union AIER0_T
{
	io_byte REG;
	struct
	{
		io_byte AIER00:1;		/* Address match interrupt 0 enable bit */
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} AIER0;
#define		AIER0		(*(volatile union AIER0_T *) 0x01C3)

/*------------------------------------------------------------------------------------
  Address Match Interrupt Enable Register 1
------------------------------------------------------------------------------------*/
typedef union AIER1_T
{
	io_byte REG;
	struct
	{
		io_byte AIER10:1;		/* Address match interrupt 1 enable bit*/
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} AIER1;
#define		AIER1		(*(volatile union AIER1_T *) 0x01C7)

/*------------------------------------------------------------------------------------
  Pull-Up Control Register 0
------------------------------------------------------------------------------------*/
typedef union PUR0_T
{
	io_byte REG;
	struct
	{
		io_byte PU00:1;		/* P00 to P03 pull-up */
		io_byte PU01:1;		/* P04 to P07 pull-up */
		io_byte PU02:1;		/* P10 to P13 pull-up */
		io_byte PU03:1;		/* P14 to P17 pull-up */
		io_byte PU04:1;		/* P20 to P23 pull-up */
		io_byte PU05:1;		/* P24 to P27 pull-up */
		io_byte PU06:1;		/* P30 to P33 pull-up */
		io_byte PU07:1;		/* P34 to P37 pull-up */
	} BIT;
} PUR0;
#define		PUR0		(*(volatile union PUR0_T *) 0x01E0)

/*------------------------------------------------------------------------------------
  Pull-Up Control Register 1
------------------------------------------------------------------------------------*/
typedef union PUR1_T
{
	io_byte REG;
	struct
	{
		io_byte PU10:1;		/* P43 pull-up */
		io_byte PU11:1;		/* P44 to P47 pull-up */
		io_byte PU12:1;		/* P50 to P53 pull-up */
		io_byte PU13:1;		/* P54, P56, P57 pull-up */
		io_byte PU14:1;		/* P60 to P63 pull-up */
		io_byte PU15:1;		/* P64 to P67 pull-up */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} PUR1;
#define		PUR1		(*(volatile union PUR1_T *) 0x01E1)

/*------------------------------------------------------------------------------------
  Pull-Up Control Register 2
------------------------------------------------------------------------------------*/
typedef union PUR2_T
{
	io_byte REG;
	struct
	{
		io_byte PU20:1;		/* P80 to P83 pull-up */
		io_byte PU21:1;		/* P84 to P86 pull-up */
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} PUR2;
#define		PUR2		(*(volatile union PUR2_T *) 0x01E2)

/*------------------------------------------------------------------------------------
  Input Threshold Control Register 0
------------------------------------------------------------------------------------*/
typedef union VLT0_T
{
	io_byte REG;
	struct
	{
		io_byte VLT00:1;		/* P0 input level select bit */
		io_byte VLT01:1;		/* P0 input level select bit */
		io_byte VLT02:1;		/* P1 input level select bit */
		io_byte VLT03:1;		/* P1 input level select bit */
		io_byte VLT04:1;		/* P2 input level select bit */
		io_byte VLT05:1;		/* P2 input level select bit */
		io_byte VLT06:1;		/* P3 input level select bit */
		io_byte VLT07:1;		/* P3 input level select bit */
	} BIT;
} VLT0;
#define		VLT0		(*(volatile union VLT0_T *) 0x01F5)

/*------------------------------------------------------------------------------------
  Input Threshold Control Register 1
------------------------------------------------------------------------------------*/
typedef union VLT1_T
{
	io_byte REG;
	struct
	{
		io_byte VLT10:1;		/* P42 to P47 input level select bit */
		io_byte VLT11:1;		/* P42 to P47 input level select bit */
		io_byte VLT12:1;		/* P50 to P54, P56, P57 input level select bit */
		io_byte VLT13:1;		/* P50 to P54, P56, P57 input level select bit */
		io_byte VLT14:1;		/* P6 input level select bit */
		io_byte VLT15:1;		/* P6 input level select bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} VLT1;
#define		VLT1		(*(volatile union VLT1_T *) 0x01F6)

/*------------------------------------------------------------------------------------
  Input Threshold Control Register 2
------------------------------------------------------------------------------------*/
typedef union VLT2_T
{
	io_byte REG;
	struct
	{
		io_byte VLT20:1;		/* P80 to P86 input level select bit */
		io_byte VLT21:1;		/* P80 to P86 input level select bit */
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} VLT2;
#define		VLT2		(*(volatile union VLT2_T *) 0x01F7)

/*------------------------------------------------------------------------------------
  External Interrupt Enable Register
------------------------------------------------------------------------------------*/
typedef union INTEN_T
{
	io_byte REG;
	struct
	{
		io_byte INT0EN:1;		/* INT0 input enable bit */
		io_byte INT0PL:1;		/* INT0 input polarity select bit */
		io_byte INT1EN:1;		/* INT1 input enable bit */
		io_byte INT1PL:1;		/* INT1 input polarity select bit */
		io_byte INT2EN:1;		/* INT2 input enable bit */
		io_byte INT2PL:1;		/* INT2 input polarity select bit */
		io_byte INT3EN:1;		/* INT3 input enable bit */
		io_byte INT3PL:1;		/* INT3 input polarity select bit */
	} BIT;
} INTEN;
#define		INTEN		(*(volatile union INTEN_T *) 0x01FA)

/*------------------------------------------------------------------------------------
  External Input Enable Register 1
------------------------------------------------------------------------------------*/
typedef union INTEN1_T
{
	io_byte REG;
	struct
	{
		io_byte INT4EN:1;		/* INT4 input enable bit */
		io_byte INT4PL:1;		/* INT4 input polarity select bit */
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} INTEN1;
#define		INTEN1		(*(volatile union INTEN1_T *) 0x01FB)

/*------------------------------------------------------------------------------------
  INT Input Filter Select Register 0
------------------------------------------------------------------------------------*/
typedef union INTF_T
{
	io_byte REG;
	struct
	{
		io_byte INT0F0:1;		/* INT0 input filter select bit */
		io_byte INT0F1:1;		/* INT0 input filter select bit */
		io_byte INT1F0:1;		/* INT1 input filter select bit */
		io_byte INT1F1:1;		/* INT1 input filter select bit */
		io_byte INT2F0:1;		/* INT2 input filter select bit */
		io_byte INT2F1:1;		/* INT2 input filter select bit */
		io_byte INT3F0:1;		/* INT3 input filter select bit */
		io_byte INT3F1:1;		/* INT3 input filter select bit */
	} BIT;
} INTF;
#define		INTF		(*(volatile union INTF_T *) 0x01FC)

/*------------------------------------------------------------------------------------
  INT Input Filter Select Register 1
------------------------------------------------------------------------------------*/
typedef union INTF1_T
{
	io_byte REG;
	struct
	{
		io_byte INT4F0:1;		/* INT4 input filter select bit */
		io_byte INT4F1:1;		/* INT4 input filter select bit */
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} INTF1;
#define		INTF1		(*(volatile union INTF1_T *) 0x01FD)

/*------------------------------------------------------------------------------------
  Key Input Enable Register 0
------------------------------------------------------------------------------------*/
typedef union KIEN_T
{
	io_byte REG;
	struct
	{
		io_byte KI0EN:1;		/* KI0 input enable bit */
		io_byte KI0PL:1;		/* KI0 input polarity select bit */
		io_byte KI1EN:1;		/* KI1 input enable bit */
		io_byte KI1PL:1;		/* KI1 input polarity select bit */
		io_byte KI2EN:1;		/* KI2 input enable bit */
		io_byte KI2PL:1;		/* KI2 input polarity select bit */
		io_byte KI3EN:1;		/* KI3 input enable bit */
		io_byte KI3PL:1;		/* KI3 input polarity select bit */
	} BIT;
} KIEN;
#define		KIEN		(*(volatile union KIEN_T *) 0x01FE)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 0 (INT0)
------------------------------------------------------------------------------------*/
typedef union DTCVCT0_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT0;
#define		DTCVCT0		(*(volatile union DTCVCT0_T *) 0x2C00)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 1 (INT1)
------------------------------------------------------------------------------------*/
typedef union DTCVCT1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT1;
#define		DTCVCT1		(*(volatile union DTCVCT1_T *) 0x2C01)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 2 (INT2)
------------------------------------------------------------------------------------*/
typedef union DTCVCT2_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT2;
#define		DTCVCT2		(*(volatile union DTCVCT2_T *) 0x2C02)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 3 (INT3)
------------------------------------------------------------------------------------*/
typedef union DTCVCT3_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT3;
#define		DTCVCT3		(*(volatile union DTCVCT3_T *) 0x2C03)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 4 (INT4)
------------------------------------------------------------------------------------*/
typedef union DTCVCT4_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT4;
#define		DTCVCT4		(*(volatile union DTCVCT4_T *) 0x2C04)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 5
------------------------------------------------------------------------------------*/
typedef union DTCVCT5_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT5;
#define		DTCVCT5		(*(volatile union DTCVCT5_T *) 0x2C05)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 6
------------------------------------------------------------------------------------*/
typedef union DTCVCT6_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT6;
#define		DTCVCT6		(*(volatile union DTCVCT6_T *) 0x2C06)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 7
------------------------------------------------------------------------------------*/
typedef union DTCVCT7_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT7;
#define		DTCVCT7		(*(volatile union DTCVCT7_T *) 0x2C07)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 8 (Key Input)
------------------------------------------------------------------------------------*/
typedef union DTCVCT8_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT8;
#define		DTCVCT8		(*(volatile union DTCVCT8_T *) 0x2C08)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 9 (A/D)
------------------------------------------------------------------------------------*/
typedef union DTCVCT9_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT9;
#define		DTCVCT9		(*(volatile union DTCVCT9_T *) 0x2C09)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 10 (Uart0 Receive)
------------------------------------------------------------------------------------*/
typedef union DTCVCT10_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT10;
#define		DTCVCT10		(*(volatile union DTCVCT10_T *) 0x2C0A)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 11 (Uart0 Transfer)
------------------------------------------------------------------------------------*/
typedef union DTCVCT11_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT11;
#define		DTCVCT11		(*(volatile union DTCVCT11_T *) 0x2C0B)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 12
------------------------------------------------------------------------------------*/
typedef union DTCVCT12_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT12;
#define		DTCVCT12		(*(volatile union DTCVCT12_T *) 0x2C0C)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 13
------------------------------------------------------------------------------------*/
typedef union DTCVCT13_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT13;
#define		DTCVCT13		(*(volatile union DTCVCT13_T *) 0x2C0D)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 14 (Uart2 Receive)
------------------------------------------------------------------------------------*/
typedef union DTCVCT14_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT14;
#define		DTCVCT14		(*(volatile union DTCVCT14_T *) 0x2C0E)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 15 (Uart2 Transfer)
------------------------------------------------------------------------------------*/
typedef union DTCVCT15_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT15;
#define		DTCVCT15		(*(volatile union DTCVCT15_T *) 0x2C0F)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 16 (SSU Receive data Register full)
------------------------------------------------------------------------------------*/
typedef union DTCVCT16_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT16;
#define		DTCVCT16		(*(volatile union DTCVCT16_T *) 0x2C10)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 17 (SSU Transmit data empty)
------------------------------------------------------------------------------------*/
typedef union DTCVCT17_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT17;
#define		DTCVCT17		(*(volatile union DTCVCT17_T *) 0x2C11)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 18 (Voltage Monitor Circuit 2)
------------------------------------------------------------------------------------*/
typedef union DTCVCT18_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT18;
#define		DTCVCT18		(*(volatile union DTCVCT18_T *) 0x2C12)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 19 (Voltage Monitor Circuit 1)
------------------------------------------------------------------------------------*/
typedef union DTCVCT19_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT19;
#define		DTCVCT19		(*(volatile union DTCVCT19_T *) 0x2C13)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 20
------------------------------------------------------------------------------------*/
typedef union DTCVCT20_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT20;
#define		DTCVCT20		(*(volatile union DTCVCT20_T *) 0x2C14)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 21
------------------------------------------------------------------------------------*/
typedef union DTCVCT21_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT21;
#define		DTCVCT21		(*(volatile union DTCVCT21_T *) 0x2C15)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 22 (TRC Input capture / compare match A)
------------------------------------------------------------------------------------*/
typedef union DTCVCT22_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT22;
#define		DTCVCT22		(*(volatile union DTCVCT22_T *) 0x2C16)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 23 (TRC Input capture / compare match B)
------------------------------------------------------------------------------------*/
typedef union DTCVCT23_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT23;
#define		DTCVCT23		(*(volatile union DTCVCT23_T *) 0x2C17)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 24 (TRC Input capture / compare match C)
------------------------------------------------------------------------------------*/
typedef union DTCVCT24_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT24;
#define		DTCVCT24		(*(volatile union DTCVCT24_T *) 0x2C18)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 25 (TRC Input capture / compare match D)
------------------------------------------------------------------------------------*/
typedef union DTCVCT25_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT25;
#define		DTCVCT25		(*(volatile union DTCVCT25_T *) 0x2C19)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 26 (TRD0 Input capture / compare match A)
------------------------------------------------------------------------------------*/
typedef union DTCVCT26_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT26;
#define		DTCVCT26		(*(volatile union DTCVCT26_T *) 0x2C1A)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 27 (TRD0 Input capture / compare match B)
------------------------------------------------------------------------------------*/
typedef union DTCVCT27_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT27;
#define		DTCVCT27		(*(volatile union DTCVCT27_T *) 0x2C1B)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 28 (TRD0 Input capture / compare match C)
------------------------------------------------------------------------------------*/
typedef union DTCVCT28_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT28;
#define		DTCVCT28		(*(volatile union DTCVCT28_T *) 0x2C1C)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 29 (TRD0 Input capture / compare match D)
------------------------------------------------------------------------------------*/
typedef union DTCVCT29_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT29;
#define		DTCVCT29		(*(volatile union DTCVCT29_T *) 0x2C1D)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 30 (TRD1 Input capture / compare match A)
------------------------------------------------------------------------------------*/
typedef union DTCVCT30_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT30;
#define		DTCVCT30		(*(volatile union DTCVCT30_T *) 0x2C1E)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 31 (TRD1 Input capture / compare match B)
------------------------------------------------------------------------------------*/
typedef union DTCVCT31_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT31;
#define		DTCVCT31		(*(volatile union DTCVCT31_T *) 0x2C1F)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 32 (TRD1 Input capture / compare match C)
------------------------------------------------------------------------------------*/
typedef union DTCVCT32_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT32;
#define		DTCVCT32		(*(volatile union DTCVCT32_T *) 0x2C20)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 33 (TRD1 Input capture / compare match D)
------------------------------------------------------------------------------------*/
typedef union DTCVCT33_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT33;
#define		DTCVCT33		(*(volatile union DTCVCT33_T *) 0x2C21)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 34
------------------------------------------------------------------------------------*/
typedef union DTCVCT34_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT34;
#define		DTCVCT34		(*(volatile union DTCVCT34_T *) 0x2C22)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 35
------------------------------------------------------------------------------------*/
typedef union DTCVCT35_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT35;
#define		DTCVCT35		(*(volatile union DTCVCT35_T *) 0x2C23)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 36
------------------------------------------------------------------------------------*/
typedef union DTCVCT36_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT36;
#define		DTCVCT36		(*(volatile union DTCVCT36_T *) 0x2C24)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 37
------------------------------------------------------------------------------------*/
typedef union DTCVCT37_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT37;
#define		DTCVCT37		(*(volatile union DTCVCT37_T *) 0x2C25)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 38
------------------------------------------------------------------------------------*/
typedef union DTCVCT38_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT38;
#define		DTCVCT38		(*(volatile union DTCVCT38_T *) 0x2C26)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 39
------------------------------------------------------------------------------------*/
typedef union DTCVCT39_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT39;
#define		DTCVCT39		(*(volatile union DTCVCT39_T *) 0x2C27)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 40
------------------------------------------------------------------------------------*/
typedef union DTCVCT40_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT40;
#define		DTCVCT40		(*(volatile union DTCVCT40_T *) 0x2C28)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 41
------------------------------------------------------------------------------------*/
typedef union DTCVCT41_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT41;
#define		DTCVCT41		(*(volatile union DTCVCT41_T *) 0x2C29)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 42 (TRE)
------------------------------------------------------------------------------------*/
typedef union DTCVCT42_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT42;
#define		DTCVCT42		(*(volatile union DTCVCT42_T *) 0x2C2A)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 43
------------------------------------------------------------------------------------*/
typedef union DTCVCT43_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT43;
#define		DTCVCT43		(*(volatile union DTCVCT43_T *) 0x2C2B)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 44
------------------------------------------------------------------------------------*/
typedef union DTCVCT44_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT44;
#define		DTCVCT44		(*(volatile union DTCVCT44_T *) 0x2C2C)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 45
------------------------------------------------------------------------------------*/
typedef union DTCVCT45_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT45;
#define		DTCVCT45		(*(volatile union DTCVCT45_T *) 0x2C2D)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 46
------------------------------------------------------------------------------------*/
typedef union DTCVCT46_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT46;
#define		DTCVCT46		(*(volatile union DTCVCT46_T *) 0x2C2E)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 47
------------------------------------------------------------------------------------*/
typedef union DTCVCT47_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT47;
#define		DTCVCT47		(*(volatile union DTCVCT47_T *) 0x2C2F)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 48
------------------------------------------------------------------------------------*/
typedef union DTCVCT48_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT48;
#define		DTCVCT48		(*(volatile union DTCVCT48_T *) 0x2C30)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 49 (TRA)
------------------------------------------------------------------------------------*/
typedef union DTCVCT49_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT49;
#define		DTCVCT49		(*(volatile union DTCVCT49_T *) 0x2C31)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 50
------------------------------------------------------------------------------------*/
typedef union DTCVCT50_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT50;
#define		DTCVCT50		(*(volatile union DTCVCT50_T *) 0x2C32)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 51 (TRB)
------------------------------------------------------------------------------------*/
typedef union DTCVCT51_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT51;
#define		DTCVCT51		(*(volatile union DTCVCT51_T *) 0x2C33)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 52 (Flash memory ready)
------------------------------------------------------------------------------------*/
typedef union DTCVCT52_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT52;
#define		DTCVCT52		(*(volatile union DTCVCT52_T *) 0x2C34)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 53
------------------------------------------------------------------------------------*/
typedef union DTCVCT53_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT53;
#define		DTCVCT53		(*(volatile union DTCVCT53_T *) 0x2C35)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 54
------------------------------------------------------------------------------------*/
typedef union DTCVCT54_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT54;
#define		DTCVCT54		(*(volatile union DTCVCT54_T *) 0x2C36)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 55
------------------------------------------------------------------------------------*/
typedef union DTCVCT55_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT55;
#define		DTCVCT55		(*(volatile union DTCVCT55_T *) 0x2C37)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 56
------------------------------------------------------------------------------------*/
typedef union DTCVCT56_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT56;
#define		DTCVCT56		(*(volatile union DTCVCT56_T *) 0x2C38)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 57
------------------------------------------------------------------------------------*/
typedef union DTCVCT57_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT57;
#define		DTCVCT57		(*(volatile union DTCVCT57_T *) 0x2C39)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 58
------------------------------------------------------------------------------------*/
typedef union DTCVCT58_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT58;
#define		DTCVCT58		(*(volatile union DTCVCT58_T *) 0x2C3A)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 59
------------------------------------------------------------------------------------*/
typedef union DTCVCT59_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT59;
#define		DTCVCT59		(*(volatile union DTCVCT59_T *) 0x2C3B)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 60
------------------------------------------------------------------------------------*/
typedef union DTCVCT60_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT60;
#define		DTCVCT60		(*(volatile union DTCVCT60_T *) 0x2C3C)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 61
------------------------------------------------------------------------------------*/
typedef union DTCVCT61_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT61;
#define		DTCVCT61		(*(volatile union DTCVCT61_T *) 0x2C3D)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 62
------------------------------------------------------------------------------------*/
typedef union DTCVCT62_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT62;
#define		DTCVCT62		(*(volatile union DTCVCT62_T *) 0x2C3E)

/*------------------------------------------------------------------------------------
  DTC Transfer Vector Area 63
------------------------------------------------------------------------------------*/
typedef union DTCVCT63_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCVCT63;
#define		DTCVCT63		(*(volatile union DTCVCT63_T *) 0x2C3F)

/*------------------------------------------------------------------------------------
  DTC Control Register 0
------------------------------------------------------------------------------------*/
typedef union DTCCR0_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR0;
#define		DTCCR0		(*(volatile union DTCCR0_T *) 0x2C40)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 0
------------------------------------------------------------------------------------*/
typedef union DTBLS0_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS0;
#define		DTBLS0		(*(volatile union DTBLS0_T *) 0x2C41)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 0
------------------------------------------------------------------------------------*/
typedef union DTCCT0_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT0;
#define		DTCCT0		(*(volatile union DTCCT0_T *) 0x2C42)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 0
------------------------------------------------------------------------------------*/
typedef union DTRLD0_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD0;
#define		DTRLD0		(*(volatile union DTRLD0_T *) 0x2C43)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 0
------------------------------------------------------------------------------------*/
typedef union DTSAR0_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR0;
#define		DTSAR0		(*(volatile union DTSAR0_T *) 0x2C44)

/*------------------------------------------------------------------------------------
  DTC Destination Register 0
------------------------------------------------------------------------------------*/
typedef union DTDAR0_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR0;
#define		DTDAR0		(*(volatile union DTDAR0_T *) 0x2C46)

/*------------------------------------------------------------------------------------
  DTC Control Register 1
------------------------------------------------------------------------------------*/
typedef union DTCCR1_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR1;
#define		DTCCR1		(*(volatile union DTCCR1_T *) 0x2C48)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 1
------------------------------------------------------------------------------------*/
typedef union DTBLS1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS1;
#define		DTBLS1		(*(volatile union DTBLS1_T *) 0x2C49)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 1
------------------------------------------------------------------------------------*/
typedef union DTCCT1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT1;
#define		DTCCT1		(*(volatile union DTCCT1_T *) 0x2C4A)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 1
------------------------------------------------------------------------------------*/
typedef union DTRLD1_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD1;
#define		DTRLD1		(*(volatile union DTRLD1_T *) 0x2C4B)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 1
------------------------------------------------------------------------------------*/
typedef union DTSAR1_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR1;
#define		DTSAR1		(*(volatile union DTSAR1_T *) 0x2C4C)

/*------------------------------------------------------------------------------------
  DTC Destination Register 1
------------------------------------------------------------------------------------*/
typedef union DTDAR1_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR1;
#define		DTDAR1		(*(volatile union DTDAR1_T *) 0x2C4E)

/*------------------------------------------------------------------------------------
  DTC Control Register 2
------------------------------------------------------------------------------------*/
typedef union DTCCR2_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR2;
#define		DTCCR2		(*(volatile union DTCCR2_T *) 0x2C50)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 2
------------------------------------------------------------------------------------*/
typedef union DTBLS2_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS2;
#define		DTBLS2		(*(volatile union DTBLS2_T *) 0x2C51)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 2
------------------------------------------------------------------------------------*/
typedef union DTCCT2_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT2;
#define		DTCCT2		(*(volatile union DTCCT2_T *) 0x2C52)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 2
------------------------------------------------------------------------------------*/
typedef union DTRLD2_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD2;
#define		DTRLD2		(*(volatile union DTRLD2_T *) 0x2C53)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 2
------------------------------------------------------------------------------------*/
typedef union DTSAR2_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR2;
#define		DTSAR2		(*(volatile union DTSAR2_T *) 0x2C54)

/*------------------------------------------------------------------------------------
  DTC Destination Register 2
------------------------------------------------------------------------------------*/
typedef union DTDAR2_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR2;
#define		DTDAR2		(*(volatile union DTDAR2_T *) 0x2C56)

/*------------------------------------------------------------------------------------
  DTC Control Register 3
------------------------------------------------------------------------------------*/
typedef union DTCCR3_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR3;
#define		DTCCR3		(*(volatile union DTCCR3_T *) 0x2C58)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 3
------------------------------------------------------------------------------------*/
typedef union DTBLS3_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS3;
#define		DTBLS3		(*(volatile union DTBLS3_T *) 0x2C59)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 3
------------------------------------------------------------------------------------*/
typedef union DTCCT3_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT3;
#define		DTCCT3		(*(volatile union DTCCT3_T *) 0x2C5A)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 3
------------------------------------------------------------------------------------*/
typedef union DTRLD3_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD3;
#define		DTRLD3		(*(volatile union DTRLD3_T *) 0x2C5B)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 3
------------------------------------------------------------------------------------*/
typedef union DTSAR3_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR3;
#define		DTSAR3		(*(volatile union DTSAR3_T *) 0x2C5C)

/*------------------------------------------------------------------------------------
  DTC Destination Register 3
------------------------------------------------------------------------------------*/
typedef union DTDAR3_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR3;
#define		DTDAR3		(*(volatile union DTDAR3_T *) 0x2C5E)

/*------------------------------------------------------------------------------------
  DTC Control Register 4
------------------------------------------------------------------------------------*/
typedef union DTCCR4_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR4;
#define		DTCCR4		(*(volatile union DTCCR4_T *) 0x2C60)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 4
------------------------------------------------------------------------------------*/
typedef union DTBLS4_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS4;
#define		DTBLS4		(*(volatile union DTBLS4_T *) 0x2C61)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 4
------------------------------------------------------------------------------------*/
typedef union DTCCT4_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT4;
#define		DTCCT4		(*(volatile union DTCCT4_T *) 0x2C62)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 4
------------------------------------------------------------------------------------*/
typedef union DTRLD4_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD4;
#define		DTRLD4		(*(volatile union DTRLD4_T *) 0x2C63)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 4
------------------------------------------------------------------------------------*/
typedef union DTSAR4_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR4;
#define		DTSAR4		(*(volatile union DTSAR4_T *) 0x2C64)

/*------------------------------------------------------------------------------------
  DTC Destination Register 4
------------------------------------------------------------------------------------*/
typedef union DTDAR4_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR4;
#define		DTDAR4		(*(volatile union DTDAR4_T *) 0x2C66)

/*------------------------------------------------------------------------------------
  DTC Control Register 5
------------------------------------------------------------------------------------*/
typedef union DTCCR5_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR5;
#define		DTCCR5		(*(volatile union DTCCR5_T *) 0x2C68)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 5
------------------------------------------------------------------------------------*/
typedef union DTBLS5_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS5;
#define		DTBLS5		(*(volatile union DTBLS5_T *) 0x2C69)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 5
------------------------------------------------------------------------------------*/
typedef union DTCCT5_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT5;
#define		DTCCT5		(*(volatile union DTCCT5_T *) 0x2C6A)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 5
------------------------------------------------------------------------------------*/
typedef union DTRLD5_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD5;
#define		DTRLD5		(*(volatile union DTRLD5_T *) 0x2C6B)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 5
------------------------------------------------------------------------------------*/
typedef union DTSAR5_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR5;
#define		DTSAR5		(*(volatile union DTSAR5_T *) 0x2C6C)

/*------------------------------------------------------------------------------------
  DTC Destination Register 5
------------------------------------------------------------------------------------*/
typedef union DTDAR5_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR5;
#define		DTDAR5		(*(volatile union DTDAR5_T *) 0x2C6E)

/*------------------------------------------------------------------------------------
  DTC Control Register 6
------------------------------------------------------------------------------------*/
typedef union DTCCR6_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR6;
#define		DTCCR6		(*(volatile union DTCCR6_T *) 0x2C70)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 6
------------------------------------------------------------------------------------*/
typedef union DTBLS6_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS6;
#define		DTBLS6		(*(volatile union DTBLS6_T *) 0x2C71)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 6
------------------------------------------------------------------------------------*/
typedef union DTCCT6_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT6;
#define		DTCCT6		(*(volatile union DTCCT6_T *) 0x2C72)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 6
------------------------------------------------------------------------------------*/
typedef union DTRLD6_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD6;
#define		DTRLD6		(*(volatile union DTRLD6_T *) 0x2C73)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 6
------------------------------------------------------------------------------------*/
typedef union DTSAR6_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR6;
#define		DTSAR6		(*(volatile union DTSAR6_T *) 0x2C74)

/*------------------------------------------------------------------------------------
  DTC Destination Register 6
------------------------------------------------------------------------------------*/
typedef union DTDAR6_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR6;
#define		DTDAR6		(*(volatile union DTDAR6_T *) 0x2C76)

/*------------------------------------------------------------------------------------
  DTC Control Register 7
------------------------------------------------------------------------------------*/
typedef union DTCCR7_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR7;
#define		DTCCR7		(*(volatile union DTCCR7_T *) 0x2C78)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 7
------------------------------------------------------------------------------------*/
typedef union DTBLS7_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS7;
#define		DTBLS7		(*(volatile union DTBLS7_T *) 0x2C79)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 7
------------------------------------------------------------------------------------*/
typedef union DTCCT7_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT7;
#define		DTCCT7		(*(volatile union DTCCT7_T *) 0x2C7A)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 7
------------------------------------------------------------------------------------*/
typedef union DTRLD7_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD7;
#define		DTRLD7		(*(volatile union DTRLD7_T *) 0x2C7B)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 7
------------------------------------------------------------------------------------*/
typedef union DTSAR7_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR7;
#define		DTSAR7		(*(volatile union DTSAR7_T *) 0x2C7C)

/*------------------------------------------------------------------------------------
  DTC Destination Register 7
------------------------------------------------------------------------------------*/
typedef union DTDAR7_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR7;
#define		DTDAR7		(*(volatile union DTDAR7_T *) 0x2C7E)

/*------------------------------------------------------------------------------------
  DTC Control Register 8
------------------------------------------------------------------------------------*/
typedef union DTCCR8_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR8;
#define		DTCCR8		(*(volatile union DTCCR8_T *) 0x2C80)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 8
------------------------------------------------------------------------------------*/
typedef union DTBLS8_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS8;
#define		DTBLS8		(*(volatile union DTBLS8_T *) 0x2C81)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 8
------------------------------------------------------------------------------------*/
typedef union DTCCT8_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT8;
#define		DTCCT8		(*(volatile union DTCCT8_T *) 0x2C82)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 8
------------------------------------------------------------------------------------*/
typedef union DTRLD8_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD8;
#define		DTRLD8		(*(volatile union DTRLD8_T *) 0x2C83)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 8
------------------------------------------------------------------------------------*/
typedef union DTSAR8_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR8;
#define		DTSAR8		(*(volatile union DTSAR8_T *) 0x2C84)

/*------------------------------------------------------------------------------------
  DTC Destination Register 8
------------------------------------------------------------------------------------*/
typedef union DTDAR8_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR8;
#define		DTDAR8		(*(volatile union DTDAR8_T *) 0x2C86)

/*------------------------------------------------------------------------------------
  DTC Control Register 9
------------------------------------------------------------------------------------*/
typedef union DTCCR9_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR9;
#define		DTCCR9		(*(volatile union DTCCR9_T *) 0x2C88)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 9
------------------------------------------------------------------------------------*/
typedef union DTBLS9_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS9;
#define		DTBLS9		(*(volatile union DTBLS9_T *) 0x2C89)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 9
------------------------------------------------------------------------------------*/
typedef union DTCCT9_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT9;
#define		DTCCT9		(*(volatile union DTCCT9_T *) 0x2C8A)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 9
------------------------------------------------------------------------------------*/
typedef union DTRLD9_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD9;
#define		DTRLD9		(*(volatile union DTRLD9_T *) 0x2C8B)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 9
------------------------------------------------------------------------------------*/
typedef union DTSAR9_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR9;
#define		DTSAR9		(*(volatile union DTSAR9_T *) 0x2C8C)

/*------------------------------------------------------------------------------------
  DTC Destination Register 9
------------------------------------------------------------------------------------*/
typedef union DTDAR9_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR9;
#define		DTDAR9		(*(volatile union DTDAR9_T *) 0x2C8E)

/*------------------------------------------------------------------------------------
  DTC Control Register 10
------------------------------------------------------------------------------------*/
typedef union DTCCR10_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR10;
#define		DTCCR10		(*(volatile union DTCCR10_T *) 0x2C90)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 10
------------------------------------------------------------------------------------*/
typedef union DTBLS10_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS10;
#define		DTBLS10		(*(volatile union DTBLS10_T *) 0x2C91)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 10
------------------------------------------------------------------------------------*/
typedef union DTCCT10_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT10;
#define		DTCCT10		(*(volatile union DTCCT10_T *) 0x2C92)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 10
------------------------------------------------------------------------------------*/
typedef union DTRLD10_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD10;
#define		DTRLD10		(*(volatile union DTRLD10_T *) 0x2C93)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 10
------------------------------------------------------------------------------------*/
typedef union DTSAR10_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR10;
#define		DTSAR10		(*(volatile union DTSAR10_T *) 0x2C94)

/*------------------------------------------------------------------------------------
  DTC Destination Register 10
------------------------------------------------------------------------------------*/
typedef union DTDAR10_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR10;
#define		DTDAR10		(*(volatile union DTDAR10_T *) 0x2C96)

/*------------------------------------------------------------------------------------
  DTC Control Register 11
------------------------------------------------------------------------------------*/
typedef union DTCCR11_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR11;
#define		DTCCR11		(*(volatile union DTCCR11_T *) 0x2C98)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 11
------------------------------------------------------------------------------------*/
typedef union DTBLS11_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS11;
#define		DTBLS11		(*(volatile union DTBLS11_T *) 0x2C99)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 11
------------------------------------------------------------------------------------*/
typedef union DTCCT11_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT11;
#define		DTCCT11		(*(volatile union DTCCT11_T *) 0x2C9A)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 11
------------------------------------------------------------------------------------*/
typedef union DTRLD11_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD11;
#define		DTRLD11		(*(volatile union DTRLD11_T *) 0x2C9B)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 11
------------------------------------------------------------------------------------*/
typedef union DTSAR11_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR11;
#define		DTSAR11		(*(volatile union DTSAR11_T *) 0x2C9C)

/*------------------------------------------------------------------------------------
  DTC Destination Register 11
------------------------------------------------------------------------------------*/
typedef union DTDAR11_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR11;
#define		DTDAR11		(*(volatile union DTDAR11_T *) 0x2C9E)

/*------------------------------------------------------------------------------------
  DTC Control Register 12
------------------------------------------------------------------------------------*/
typedef union DTCCR12_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR12;
#define		DTCCR12		(*(volatile union DTCCR12_T *) 0x2CA0)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 12
------------------------------------------------------------------------------------*/
typedef union DTBLS12_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS12;
#define		DTBLS12		(*(volatile union DTBLS12_T *) 0x2CA1)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 12
------------------------------------------------------------------------------------*/
typedef union DTCCT12_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT12;
#define		DTCCT12		(*(volatile union DTCCT12_T *) 0x2CA2)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 12
------------------------------------------------------------------------------------*/
typedef union DTRLD12_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD12;
#define		DTRLD12		(*(volatile union DTRLD12_T *) 0x2CA3)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 12
------------------------------------------------------------------------------------*/
typedef union DTSAR12_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR12;
#define		DTSAR12		(*(volatile union DTSAR12_T *) 0x2CA4)

/*------------------------------------------------------------------------------------
  DTC Destination Register 12
------------------------------------------------------------------------------------*/
typedef union DTDAR12_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR12;
#define		DTDAR12		(*(volatile union DTDAR12_T *) 0x2CA6)

/*------------------------------------------------------------------------------------
  DTC Control Register 13
------------------------------------------------------------------------------------*/
typedef union DTCCR13_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR13;
#define		DTCCR13		(*(volatile union DTCCR13_T *) 0x2CA8)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 13
------------------------------------------------------------------------------------*/
typedef union DTBLS13_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS13;
#define		DTBLS13		(*(volatile union DTBLS13_T *) 0x2CA9)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 13
------------------------------------------------------------------------------------*/
typedef union DTCCT13_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT13;
#define		DTCCT13		(*(volatile union DTCCT13_T *) 0x2CAA)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 13
------------------------------------------------------------------------------------*/
typedef union DTRLD13_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD13;
#define		DTRLD13		(*(volatile union DTRLD13_T *) 0x2CAB)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 13
------------------------------------------------------------------------------------*/
typedef union DTSAR13_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR13;
#define		DTSAR13		(*(volatile union DTSAR13_T *) 0x2CAC)

/*------------------------------------------------------------------------------------
  DTC Destination Register 13
------------------------------------------------------------------------------------*/
typedef union DTDAR13_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR13;
#define		DTDAR13		(*(volatile union DTDAR13_T *) 0x2CAE)

/*------------------------------------------------------------------------------------
  DTC Control Register 14
------------------------------------------------------------------------------------*/
typedef union DTCCR14_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR14;
#define		DTCCR14		(*(volatile union DTCCR14_T *) 0x2CB0)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 14
------------------------------------------------------------------------------------*/
typedef union DTBLS14_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS14;
#define		DTBLS14		(*(volatile union DTBLS14_T *) 0x2CB1)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 14
------------------------------------------------------------------------------------*/
typedef union DTCCT14_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT14;
#define		DTCCT14		(*(volatile union DTCCT14_T *) 0x2CB2)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 14
------------------------------------------------------------------------------------*/
typedef union DTRLD14_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD14;
#define		DTRLD14		(*(volatile union DTRLD14_T *) 0x2CB3)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 14
------------------------------------------------------------------------------------*/
typedef union DTSAR14_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR14;
#define		DTSAR14		(*(volatile union DTSAR14_T *) 0x2CB4)

/*------------------------------------------------------------------------------------
  DTC Destination Register 14
------------------------------------------------------------------------------------*/
typedef union DTDAR14_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR14;
#define		DTDAR14		(*(volatile union DTDAR14_T *) 0x2CB6)

/*------------------------------------------------------------------------------------
  DTC Control Register 15
------------------------------------------------------------------------------------*/
typedef union DTCCR15_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR15;
#define		DTCCR15		(*(volatile union DTCCR15_T *) 0x2CB8)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 15
------------------------------------------------------------------------------------*/
typedef union DTBLS15_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS15;
#define		DTBLS15		(*(volatile union DTBLS15_T *) 0x2CB9)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 15
------------------------------------------------------------------------------------*/
typedef union DTCCT15_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT15;
#define		DTCCT15		(*(volatile union DTCCT15_T *) 0x2CBA)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 15
------------------------------------------------------------------------------------*/
typedef union DTRLD15_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD15;
#define		DTRLD15		(*(volatile union DTRLD15_T *) 0x2CBB)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 15
------------------------------------------------------------------------------------*/
typedef union DTSAR15_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR15;
#define		DTSAR15		(*(volatile union DTSAR15_T *) 0x2CBC)

/*------------------------------------------------------------------------------------
  DTC Destination Register 15
------------------------------------------------------------------------------------*/
typedef union DTDAR15_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR15;
#define		DTDAR15		(*(volatile union DTDAR15_T *) 0x2CBE)

/*------------------------------------------------------------------------------------
  DTC Control Register 16
------------------------------------------------------------------------------------*/
typedef union DTCCR16_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR16;
#define		DTCCR16		(*(volatile union DTCCR16_T *) 0x2CC0)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 16
------------------------------------------------------------------------------------*/
typedef union DTBLS16_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS16;
#define		DTBLS16		(*(volatile union DTBLS16_T *) 0x2CC1)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 16
------------------------------------------------------------------------------------*/
typedef union DTCCT16_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT16;
#define		DTCCT16		(*(volatile union DTCCT16_T *) 0x2CC2)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 16
------------------------------------------------------------------------------------*/
typedef union DTRLD16_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD16;
#define		DTRLD16		(*(volatile union DTRLD16_T *) 0x2CC3)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 16
------------------------------------------------------------------------------------*/
typedef union DTSAR16_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR16;
#define		DTSAR16		(*(volatile union DTSAR16_T *) 0x2CC4)

/*------------------------------------------------------------------------------------
  DTC Destination Register 16
------------------------------------------------------------------------------------*/
typedef union DTDAR16_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR16;
#define		DTDAR16		(*(volatile union DTDAR16_T *) 0x2CC6)

/*------------------------------------------------------------------------------------
  DTC Control Register 17
------------------------------------------------------------------------------------*/
typedef union DTCCR17_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR17;
#define		DTCCR17		(*(volatile union DTCCR17_T *) 0x2CC8)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 17
------------------------------------------------------------------------------------*/
typedef union DTBLS17_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS17;
#define		DTBLS17		(*(volatile union DTBLS17_T *) 0x2CC9)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 17
------------------------------------------------------------------------------------*/
typedef union DTCCT17_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT17;
#define		DTCCT17		(*(volatile union DTCCT17_T *) 0x2CCA)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 17
------------------------------------------------------------------------------------*/
typedef union DTRLD17_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD17;
#define		DTRLD17		(*(volatile union DTRLD17_T *) 0x2CCB)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 17
------------------------------------------------------------------------------------*/
typedef union DTSAR17_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR17;
#define		DTSAR17		(*(volatile union DTSAR17_T *) 0x2CCC)

/*------------------------------------------------------------------------------------
  DTC Destination Register 17
------------------------------------------------------------------------------------*/
typedef union DTDAR17_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR17;
#define		DTDAR17		(*(volatile union DTDAR17_T *) 0x2CCE)

/*------------------------------------------------------------------------------------
  DTC Control Register 18
------------------------------------------------------------------------------------*/
typedef union DTCCR18_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR18;
#define		DTCCR18		(*(volatile union DTCCR18_T *) 0x2CD0)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 18
------------------------------------------------------------------------------------*/
typedef union DTBLS18_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS18;
#define		DTBLS18		(*(volatile union DTBLS18_T *) 0x2CD1)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 18
------------------------------------------------------------------------------------*/
typedef union DTCCT18_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT18;
#define		DTCCT18		(*(volatile union DTCCT18_T *) 0x2CD2)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 18
------------------------------------------------------------------------------------*/
typedef union DTRLD18_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD18;
#define		DTRLD18		(*(volatile union DTRLD18_T *) 0x2CD3)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 18
------------------------------------------------------------------------------------*/
typedef union DTSAR18_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR18;
#define		DTSAR18		(*(volatile union DTSAR18_T *) 0x2CD4)

/*------------------------------------------------------------------------------------
  DTC Destination Register 18
------------------------------------------------------------------------------------*/
typedef union DTDAR18_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR18;
#define		DTDAR18		(*(volatile union DTDAR18_T *) 0x2CD6)

/*------------------------------------------------------------------------------------
  DTC Control Register 19
------------------------------------------------------------------------------------*/
typedef union DTCCR19_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR19;
#define		DTCCR19		(*(volatile union DTCCR19_T *) 0x2CD8)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 19
------------------------------------------------------------------------------------*/
typedef union DTBLS19_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS19;
#define		DTBLS19		(*(volatile union DTBLS19_T *) 0x2CD9)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 19
------------------------------------------------------------------------------------*/
typedef union DTCCT19_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT19;
#define		DTCCT19		(*(volatile union DTCCT19_T *) 0x2CDA)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 19
------------------------------------------------------------------------------------*/
typedef union DTRLD19_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD19;
#define		DTRLD19		(*(volatile union DTRLD19_T *) 0x2CDB)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 19
------------------------------------------------------------------------------------*/
typedef union DTSAR19_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR19;
#define		DTSAR19		(*(volatile union DTSAR19_T *) 0x2CDC)

/*------------------------------------------------------------------------------------
  DTC Destination Register 19
------------------------------------------------------------------------------------*/
typedef union DTDAR19_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR19;
#define		DTDAR19		(*(volatile union DTDAR19_T *) 0x2CDE)

/*------------------------------------------------------------------------------------
  DTC Control Register 20
------------------------------------------------------------------------------------*/
typedef union DTCCR20_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR20;
#define		DTCCR20		(*(volatile union DTCCR20_T *) 0x2CE0)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 20
------------------------------------------------------------------------------------*/
typedef union DTBLS20_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS20;
#define		DTBLS20		(*(volatile union DTBLS20_T *) 0x2CE1)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 20
------------------------------------------------------------------------------------*/
typedef union DTCCT20_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT20;
#define		DTCCT20		(*(volatile union DTCCT20_T *) 0x2CE2)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 20
------------------------------------------------------------------------------------*/
typedef union DTRLD20_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD20;
#define		DTRLD20		(*(volatile union DTRLD20_T *) 0x2CE3)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 20
------------------------------------------------------------------------------------*/
typedef union DTSAR20_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR20;
#define		DTSAR20		(*(volatile union DTSAR20_T *) 0x2CE4)

/*------------------------------------------------------------------------------------
  DTC Destination Register 20
------------------------------------------------------------------------------------*/
typedef union DTDAR20_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR20;
#define		DTDAR20		(*(volatile union DTDAR20_T *) 0x2CE6)

/*------------------------------------------------------------------------------------
  DTC Control Register 21
------------------------------------------------------------------------------------*/
typedef union DTCCR21_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR21;
#define		DTCCR21		(*(volatile union DTCCR21_T *) 0x2CE8)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 21
------------------------------------------------------------------------------------*/
typedef union DTBLS21_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS21;
#define		DTBLS21		(*(volatile union DTBLS21_T *) 0x2CE9)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 21
------------------------------------------------------------------------------------*/
typedef union DTCCT21_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT21;
#define		DTCCT21		(*(volatile union DTCCT21_T *) 0x2CEA)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 21
------------------------------------------------------------------------------------*/
typedef union DTRLD21_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD21;
#define		DTRLD21		(*(volatile union DTRLD21_T *) 0x2CEB)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 21
------------------------------------------------------------------------------------*/
typedef union DTSAR21_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR21;
#define		DTSAR21		(*(volatile union DTSAR21_T *) 0x2CEC)

/*------------------------------------------------------------------------------------
  DTC Destination Register 21
------------------------------------------------------------------------------------*/
typedef union DTDAR21_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR21;
#define		DTDAR21		(*(volatile union DTDAR21_T *) 0x2CEE)

/*------------------------------------------------------------------------------------
  DTC Control Register 22
------------------------------------------------------------------------------------*/
typedef union DTCCR22_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR22;
#define		DTCCR22		(*(volatile union DTCCR22_T *) 0x2CF0)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 22
------------------------------------------------------------------------------------*/
typedef union DTBLS22_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS22;
#define		DTBLS22		(*(volatile union DTBLS22_T *) 0x2CF1)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 22
------------------------------------------------------------------------------------*/
typedef union DTCCT22_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT22;
#define		DTCCT22		(*(volatile union DTCCT22_T *) 0x2CF2)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 22
------------------------------------------------------------------------------------*/
typedef union DTRLD22_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD22;
#define		DTRLD22		(*(volatile union DTRLD22_T *) 0x2CF3)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 22
------------------------------------------------------------------------------------*/
typedef union DTSAR22_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR22;
#define		DTSAR22		(*(volatile union DTSAR22_T *) 0x2CF4)

/*------------------------------------------------------------------------------------
  DTC Destination Register 22
------------------------------------------------------------------------------------*/
typedef union DTDAR22_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR22;
#define		DTDAR22		(*(volatile union DTDAR22_T *) 0x2CF6)

/*------------------------------------------------------------------------------------
  DTC Control Register 23
------------------------------------------------------------------------------------*/
typedef union DTCCR23_T
{
	io_byte REG;
	struct
	{
		io_byte MODE:1;		/* Transfer mode select bit */
		io_byte RPTSEL:1;		/* Repeat area select bit */
		io_byte SAMOD:1;		/* Source address control bit */
		io_byte DAMOD:1;		/* Destination address control bit */
		io_byte CHNE:1;		/* Chain transfer enable bit */
		io_byte RPTINT:1;		/* Repeat mode interrupt enable bit */
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCR23;
#define		DTCCR23		(*(volatile union DTCCR23_T *) 0x2CF8)

/*------------------------------------------------------------------------------------
  DTC Block Size Register 23
------------------------------------------------------------------------------------*/
typedef union DTBLS23_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTBLS23;
#define		DTBLS23		(*(volatile union DTBLS23_T *) 0x2CF9)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Register 23
------------------------------------------------------------------------------------*/
typedef union DTCCT23_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTCCT23;
#define		DTCCT23		(*(volatile union DTCCT23_T *) 0x2CFA)

/*------------------------------------------------------------------------------------
  DTC Transfer Count Reload Register 23
------------------------------------------------------------------------------------*/
typedef union DTRLD23_T
{
	io_byte REG;
	struct
	{
		io_byte B0:1;
		io_byte B1:1;
		io_byte B2:1;
		io_byte B3:1;
		io_byte B4:1;
		io_byte B5:1;
		io_byte B6:1;
		io_byte B7:1;
	} BIT;
} DTRLD23;
#define		DTRLD23		(*(volatile union DTRLD23_T *) 0x2CFB)

/*------------------------------------------------------------------------------------
  DTC Source Address Register 23
------------------------------------------------------------------------------------*/
typedef union DTSAR23_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTSAR23;
#define		DTSAR23		(*(volatile union DTSAR23_T *) 0x2CFC)

/*------------------------------------------------------------------------------------
  DTC Destination Register 23
------------------------------------------------------------------------------------*/
typedef union DTDAR23_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} DTDAR23;
#define		DTDAR23		(*(volatile union DTDAR23_T *) 0x2CFE)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRC_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRC;
#define		TRC		(*(volatile union TRC_T *) 0x0126)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRCGRA_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRCGRA;
#define		TRCGRA		(*(volatile union TRCGRA_T *) 0x0128)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRCGRB_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRCGRB;
#define		TRCGRB		(*(volatile union TRCGRB_T *) 0x012A)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRCGRC_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRCGRC;
#define		TRCGRC		(*(volatile union TRCGRC_T *) 0x012C)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRCGRD_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRCGRD;
#define		TRCGRD		(*(volatile union TRCGRD_T *) 0x012E)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRD0_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRD0;
#define		TRD0		(*(volatile union TRD0_T *) 0x0146)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRDGRA0_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRDGRA0;
#define		TRDGRA0		(*(volatile union TRDGRA0_T *) 0x0148)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRDGRB0_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRDGRB0;
#define		TRDGRB0		(*(volatile union TRDGRB0_T *) 0x014A)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRDGRC0_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRDGRC0;
#define		TRDGRC0		(*(volatile union TRDGRC0_T *) 0x014C)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRDGRD0_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRDGRD0;
#define		TRDGRD0		(*(volatile union TRDGRD0_T *) 0x014E)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRD1_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRD1;
#define		TRD1		(*(volatile union TRD1_T *) 0x0156)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRDGRA1_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRDGRA1;
#define		TRDGRA1		(*(volatile union TRDGRA1_T *) 0x0158)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRDGRB1_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRDGRB1;
#define		TRDGRB1		(*(volatile union TRDGRB1_T *) 0x015A)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRDGRC1_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRDGRC1;
#define		TRDGRC1		(*(volatile union TRDGRC1_T *) 0x015C)

/*------------------------------------------------------------------------------------
  Timer RC Counter Register, Timer RD Counter , General Register A,B,C,D
------------------------------------------------------------------------------------*/
typedef union TRDGRD1_T
{
	io_word REG;
	struct
	{
		io_byte LOW;
		io_byte HIGH;
	} BYTE;
} TRDGRD1;
#define		TRDGRD1		(*(volatile union TRDGRD1_T *) 0x015E)

/*------------------------------------------------------------------------------------
  Flash Memory Ready Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union FMRDYIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} FMRDYIC;
#define		FMRDYIC		(*(volatile union FMRDYIC_T *) 0x0041)

/*------------------------------------------------------------------------------------
  Timer RA1 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TRA1IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TRA1IC;
#define		TRA1IC		(*(volatile union TRA1IC_T *) 0x0042)

/*------------------------------------------------------------------------------------
  INT4 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union INT4IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} INT4IC;
#define		INT4IC		(*(volatile union INT4IC_T *) 0x0046)

/*------------------------------------------------------------------------------------
  Timer RC Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TRCIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TRCIC;
#define		TRCIC		(*(volatile union TRCIC_T *) 0x0047)

/*------------------------------------------------------------------------------------
  Timer RD0  Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TRD0IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TRD0IC;
#define		TRD0IC		(*(volatile union TRD0IC_T *) 0x0048)

/*------------------------------------------------------------------------------------
  Timer RD1  Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TRD1IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TRD1IC;
#define		TRD1IC		(*(volatile union TRD1IC_T *) 0x0049)

/*------------------------------------------------------------------------------------
  Timer RE  Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TREIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TREIC;
#define		TREIC		(*(volatile union TREIC_T *) 0x004A)

/*------------------------------------------------------------------------------------
  UART2 Transmit Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union S2TIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} S2TIC;
#define		S2TIC		(*(volatile union S2TIC_T *) 0x004B)

/*------------------------------------------------------------------------------------
  UART2 Receive Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union S2RIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} S2RIC;
#define		S2RIC		(*(volatile union S2RIC_T *) 0x004C)

/*------------------------------------------------------------------------------------
  Key Input Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union KUPIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} KUPIC;
#define		KUPIC		(*(volatile union KUPIC_T *) 0x004D)

/*------------------------------------------------------------------------------------
  A/D Conversion Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union ADIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} ADIC;
#define		ADIC		(*(volatile union ADIC_T *) 0x004E)

/*------------------------------------------------------------------------------------
  SSU Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union SSUIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} SSUIC;
#define		SSUIC		(*(volatile union SSUIC_T *) 0x004F)

/*------------------------------------------------------------------------------------
  Timer RF Compare 1 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union CMP1IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} CMP1IC;
#define		CMP1IC		(*(volatile union CMP1IC_T *) 0x0050)

/*------------------------------------------------------------------------------------
  UART0 Transmit Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union S0TIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} S0TIC;
#define		S0TIC		(*(volatile union S0TIC_T *) 0x0051)

/*------------------------------------------------------------------------------------
  UART0 Receive Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union S0RIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} S0RIC;
#define		S0RIC		(*(volatile union S0RIC_T *) 0x0052)

/*------------------------------------------------------------------------------------
  UART1 Transmit Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union S1TIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} S1TIC;
#define		S1TIC		(*(volatile union S1TIC_T *) 0x0053)

/*------------------------------------------------------------------------------------
  UART1 Receive Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union S1RIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} S1RIC;
#define		S1RIC		(*(volatile union S1RIC_T *) 0x0054)

/*------------------------------------------------------------------------------------
  INT2 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union INT2IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} INT2IC;
#define		INT2IC		(*(volatile union INT2IC_T *) 0x0055)

/*------------------------------------------------------------------------------------
  Timer RA0 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TRA0IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TRA0IC;
#define		TRA0IC		(*(volatile union TRA0IC_T *) 0x0056)

/*------------------------------------------------------------------------------------
  Timer RB Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TRBIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TRBIC;
#define		TRBIC		(*(volatile union TRBIC_T *) 0x0058)

/*------------------------------------------------------------------------------------
  INT1 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union INT1IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} INT1IC;
#define		INT1IC		(*(volatile union INT1IC_T *) 0x0059)

/*------------------------------------------------------------------------------------
  INT3 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union INT3IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} INT3IC;
#define		INT3IC		(*(volatile union INT3IC_T *) 0x005A)

/*------------------------------------------------------------------------------------
  Timer RF Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TRFIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TRFIC;
#define		TRFIC		(*(volatile union TRFIC_T *) 0x005B)

/*------------------------------------------------------------------------------------
  Timer RF Compare 0 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union CMP0IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} CMP0IC;
#define		CMP0IC		(*(volatile union CMP0IC_T *) 0x005C)

/*------------------------------------------------------------------------------------
  INT0 Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union INT0IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} INT0IC;
#define		INT0IC		(*(volatile union INT0IC_T *) 0x005D)

/*------------------------------------------------------------------------------------
  UART2 Bus Collision Detection Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union U2BCNIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} U2BCNIC;
#define		U2BCNIC		(*(volatile union U2BCNIC_T *) 0x005E)

/*------------------------------------------------------------------------------------
  Timer RF Capture Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union CAPIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} CAPIC;
#define		CAPIC		(*(volatile union CAPIC_T *) 0x005F)

/*------------------------------------------------------------------------------------
  Timer RG Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union TRGIC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} TRGIC;
#define		TRGIC		(*(volatile union TRGIC_T *) 0x006B)

/*------------------------------------------------------------------------------------
  Voltage Monitor 1 Level Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union VCMP1IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} VCMP1IC;
#define		VCMP1IC		(*(volatile union VCMP1IC_T *) 0x0072)

/*------------------------------------------------------------------------------------
  Voltage Monitor 2 Level Interrupt Control Register
------------------------------------------------------------------------------------*/
typedef union VCMP2IC_T
{
	struct
	{
		io_byte 	ILVL0:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL1:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	ILVL2:1;						/* INTERRUPT PRIORITY LEVEL SELECT BIT */
		io_byte 	IR:1;							/* INTERRUPT REQUEST BIT */
		io_byte 	POL:1;							/* POLARITY SELECT BIT */
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} VCMP2IC;
#define		VCMP2IC		(*(volatile union VCMP2IC_T *) 0x0073)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Mode Register
------------------------------------------------------------------------------------*/
typedef union U0MR_T
{
	struct
	{
		io_byte 	SMD0:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	SMD1:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	SMD2:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	CKDIR:1;						/* INTERNAL/EXTERNAL CLOCK SELECT BIT */
		io_byte 	STPS:1;							/* STOP BIT LENGTH SELECT BIT */
		io_byte 	PRY:1;							/* ODD/EVEN PARITY SELECT BIT */
		io_byte 	PRYE:1;							/* PARITY ENABLE BIT */
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} U0MR;
#define		U0MR		(*(volatile union U0MR_T *) 0x00A0)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Mode Register
------------------------------------------------------------------------------------*/
typedef union U1MR_T
{
	struct
	{
		io_byte 	SMD0:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	SMD1:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	SMD2:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	CKDIR:1;						/* INTERNAL/EXTERNAL CLOCK SELECT BIT */
		io_byte 	STPS:1;							/* STOP BIT LENGTH SELECT BIT */
		io_byte 	PRY:1;							/* ODD/EVEN PARITY SELECT BIT */
		io_byte 	PRYE:1;							/* PARITY ENABLE BIT */
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} U1MR;
#define		U1MR		(*(volatile union U1MR_T *) 0x0160)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Mode Register
------------------------------------------------------------------------------------*/
typedef union U2MR_T
{
	struct
	{
		io_byte 	SMD0:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	SMD1:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	SMD2:1;							/* SERIAL I/O MODE SELECT BIT */
		io_byte 	CKDIR:1;						/* INTERNAL/EXTERNAL CLOCK SELECT BIT */
		io_byte 	STPS:1;							/* STOP BIT LENGTH SELECT BIT */
		io_byte 	PRY:1;							/* ODD/EVEN PARITY SELECT BIT */
		io_byte 	PRYE:1;							/* PARITY ENABLE BIT */
		io_byte 	B7:1;
	} BIT;
	io_byte REG;
} U2MR;
#define		U2MR		(*(volatile union U2MR_T *) 0x00A8)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Control Register0
------------------------------------------------------------------------------------*/
typedef union U0C0_T
{
	struct
	{
		io_byte 	CLK0:1;							/* BRG COUNT SOURCE SELECT BIT */
		io_byte 	CLK1:1;							/* BRG COUNT SOURCE SELECT BIT */
		io_byte 	CRS:1;							/* CTS/RTS SELECT BIT */
		io_byte 	TXEPT:1;						/* TRANSMIT REGISTER EMPTY FLAG */
		io_byte 	CRD:1;							/* CTS/RTS DISABLE BIT */
		io_byte 	NCH:1;							/* DATA OUTPUT SELECT BIT */
		io_byte 	CKPOL:1;						/* CLK POLARITY SELECT BIT */
		io_byte 	UFORM:1;						 /* TRANSFER FORMAT SELECT BIT */
	} BIT;
	io_byte REG;
} U0C0;
#define		U0C0		(*(volatile union U0C0_T *) 0x00A4)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Control Register0
------------------------------------------------------------------------------------*/
typedef union U1C0_T
{
	struct
	{
		io_byte 	CLK0:1;							/* BRG COUNT SOURCE SELECT BIT */
		io_byte 	CLK1:1;							/* BRG COUNT SOURCE SELECT BIT */
		io_byte 	CRS:1;							/* CTS/RTS SELECT BIT */
		io_byte 	TXEPT:1;						/* TRANSMIT REGISTER EMPTY FLAG */
		io_byte 	CRD:1;							/* CTS/RTS DISABLE BIT */
		io_byte 	NCH:1;							/* DATA OUTPUT SELECT BIT */
		io_byte 	CKPOL:1;						/* CLK POLARITY SELECT BIT */
		io_byte 	UFORM:1;						 /* TRANSFER FORMAT SELECT BIT */
	} BIT;
	io_byte REG;
} U1C0;
#define		U1C0		(*(volatile union U1C0_T *) 0x0164)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Control Register0
------------------------------------------------------------------------------------*/
typedef union U2C0_T
{
	struct
	{
		io_byte 	CLK0:1;							/* BRG COUNT SOURCE SELECT BIT */
		io_byte 	CLK1:1;							/* BRG COUNT SOURCE SELECT BIT */
		io_byte 	CRS:1;							/* CTS/RTS SELECT BIT */
		io_byte 	TXEPT:1;						/* TRANSMIT REGISTER EMPTY FLAG */
		io_byte 	CRD:1;							/* CTS/RTS DISABLE BIT */
		io_byte 	NCH:1;							/* DATA OUTPUT SELECT BIT */
		io_byte 	CKPOL:1;						/* CLK POLARITY SELECT BIT */
		io_byte 	UFORM:1;						 /* TRANSFER FORMAT SELECT BIT */
	} BIT;
	io_byte REG;
} U2C0;
#define		U2C0		(*(volatile union U2C0_T *) 0x00AC)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Control Register1
------------------------------------------------------------------------------------*/
typedef union U0C1_T
{
	struct
	{
		io_byte 	TE:1;							/* TRANSMIT ENABLE BIT */
		io_byte 	TI:1;							/* TRANSMIT BUFFER EMPTY FLAG */
		io_byte 	RE:1;							/* RECEIVE ENABLE BIT */
		io_byte 	RI:1;							/* RECEIVE COMPLETE FLAG */
		io_byte 	IRS:1;
		io_byte 	RRM:1;
		io_byte 	LCH:1;
		io_byte 	ERE:1;
	} BIT;
	io_byte REG;
} U0C1;
#define		U0C1		(*(volatile union U0C1_T *) 0x00A5)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Control Register1
------------------------------------------------------------------------------------*/
typedef union U1C1_T
{
	struct
	{
		io_byte 	TE:1;							/* TRANSMIT ENABLE BIT */
		io_byte 	TI:1;							/* TRANSMIT BUFFER EMPTY FLAG */
		io_byte 	RE:1;							/* RECEIVE ENABLE BIT */
		io_byte 	RI:1;							/* RECEIVE COMPLETE FLAG */
		io_byte 	IRS:1;
		io_byte 	RRM:1;
		io_byte 	LCH:1;
		io_byte 	ERE:1;
	} BIT;
	io_byte REG;
} U1C1;
#define		U1C1		(*(volatile union U1C1_T *) 0x0165)

/*------------------------------------------------------------------------------------
  UARTi Transmit/Receive Control Register1
------------------------------------------------------------------------------------*/
typedef union U2C1_T
{
	struct
	{
		io_byte 	TE:1;							/* TRANSMIT ENABLE BIT */
		io_byte 	TI:1;							/* TRANSMIT BUFFER EMPTY FLAG */
		io_byte 	RE:1;							/* RECEIVE ENABLE BIT */
		io_byte 	RI:1;							/* RECEIVE COMPLETE FLAG */
		io_byte 	IRS:1;
		io_byte 	RRM:1;
		io_byte 	LCH:1;
		io_byte 	ERE:1;
	} BIT;
	io_byte REG;
} U2C1;
#define		U2C1		(*(volatile union U2C1_T *) 0x00AD)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union U0RB_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	MPRB:1;							/* MULTIPROCESSOR SELECT BIT */
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	ABT:1;							/* ARBITRATION LOST DETECTION FLAG */
		io_byte 	OER:1;							/* OVERRUN ERROR FLAG */
		io_byte 	FER:1;							/* FRAMING ERROR FLAG */
		io_byte 	PER:1;							/* PARITY ERROR FLAG */
		io_byte 	SUM:1;							/* ERROR SUM FLAG */
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} U0RB;
#define		U0RB		(*(volatile union U0RB_T *) 0x00A6)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union U1RB_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	MPRB:1;							/* MULTIPROCESSOR SELECT BIT */
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	ABT:1;							/* ARBITRATION LOST DETECTION FLAG */
		io_byte 	OER:1;							/* OVERRUN ERROR FLAG */
		io_byte 	FER:1;							/* FRAMING ERROR FLAG */
		io_byte 	PER:1;							/* PARITY ERROR FLAG */
		io_byte 	SUM:1;							/* ERROR SUM FLAG */
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} U1RB;
#define		U1RB		(*(volatile union U1RB_T *) 0x0166)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union U2RB_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	MPRB:1;							/* MULTIPROCESSOR SELECT BIT */
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	ABT:1;							/* ARBITRATION LOST DETECTION FLAG */
		io_byte 	OER:1;							/* OVERRUN ERROR FLAG */
		io_byte 	FER:1;							/* FRAMING ERROR FLAG */
		io_byte 	PER:1;							/* PARITY ERROR FLAG */
		io_byte 	SUM:1;							/* ERROR SUM FLAG */
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} U2RB;
#define		U2RB		(*(volatile union U2RB_T *) 0x00AE)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union RMAD0_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
		io_byte 	B16:1;
		io_byte 	B17:1;
		io_byte 	B18:1;
		io_byte 	B19:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	MID;							/* MID  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
		io_byte 	NC;								/* NON USE */
	} BYTE;
	io_dword REGL;
} RMAD0;
#define		RMAD0		(*(volatile union RMAD0_T *) 0x01C0)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union RMAD1_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
		io_byte 	B16:1;
		io_byte 	B17:1;
		io_byte 	B18:1;
		io_byte 	B19:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	MID;							/* MID  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
		io_byte 	NC;								/* NON USE */
	} BYTE;
	io_dword REGL;
} RMAD1;
#define		RMAD1		(*(volatile union RMAD1_T *) 0x01C4)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union U0TB_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} U0TB;
#define		U0TB		(*(volatile union U0TB_T *) 0x00A2)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union U1TB_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} U1TB;
#define		U1TB		(*(volatile union U1TB_T *) 0x0162)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union U2TB_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} U2TB;
#define		U2TB		(*(volatile union U2TB_T *) 0x00AA)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union AD0_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} AD0;
#define		AD0		(*(volatile union AD0_T *) 0x00C0)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union AD1_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} AD1;
#define		AD1		(*(volatile union AD1_T *) 0x00C2)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union AD2_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} AD2;
#define		AD2		(*(volatile union AD2_T *) 0x00C4)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union AD3_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} AD3;
#define		AD3		(*(volatile union AD3_T *) 0x00C6)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union AD4_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} AD4;
#define		AD4		(*(volatile union AD4_T *) 0x00C8)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union AD5_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} AD5;
#define		AD5		(*(volatile union AD5_T *) 0x00CA)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union AD6_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} AD6;
#define		AD6		(*(volatile union AD6_T *) 0x00CC)

/*------------------------------------------------------------------------------------
  UARTi Receive Buffer Register
------------------------------------------------------------------------------------*/
typedef union AD7_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} AD7;
#define		AD7		(*(volatile union AD7_T *) 0x00CE)

/*------------------------------------------------------------------------------------
  SS Transmit Data Register
------------------------------------------------------------------------------------*/
typedef union SSTDR_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} SSTDR;
#define		SSTDR		(*(volatile union SSTDR_T *) 0x0194)

/*------------------------------------------------------------------------------------
  SS Receive Data Register
------------------------------------------------------------------------------------*/
typedef union SSRDR_T
{
	struct
	{
		io_byte 	B0:1;
		io_byte 	B1:1;
		io_byte 	B2:1;
		io_byte 	B3:1;
		io_byte 	B4:1;
		io_byte 	B5:1;
		io_byte 	B6:1;
		io_byte 	B7:1;
		io_byte 	B8:1;
		io_byte 	B9:1;
		io_byte 	B10:1;
		io_byte 	B11:1;
		io_byte 	B12:1;
		io_byte 	B13:1;
		io_byte 	B14:1;
		io_byte 	B15:1;
	} BIT;
	struct
	{
		io_byte 	LOW;							/* LOW  8 BIT */
		io_byte 	HIGH;							/* HIGH 8 BIT */
	} BYTE;
	io_word REG;
} SSRDR;
#define		SSRDR		(*(volatile union SSRDR_T *) 0x0196)


/*------------------------------------------------------------------------------------
  definitions for unilib
------------------------------------------------------------------------------------*/
#define P0_PIO 0x00E0
#define P0_DIR 0x00E2
#define P0_PIN 0x00E0
#define P0_PEN 0x0001
#define P1_PIO 0x00E1
#define P1_DIR 0x00E3
#define P1_PIN 0x00E1
#define P1_PEN 0x0004
#define P2_PIO 0x00E4
#define P2_DIR 0x00E6
#define P2_PIN 0x00E4
#define P2_PEN 0x0010
#define P3_PIO 0x00E5
#define P3_DIR 0x00E7
#define P3_PIN 0x00E5
#define P3_PEN 0x0040
#define P4_PIO 0x00E8
#define P4_DIR 0x00EA
#define P4_PIN 0x00E8
#define P4_PEN 0x0001
#define P5_PIO 0x00E9
#define P5_DIR 0x00EB
#define P5_PIN 0x00E9
#define P5_PEN 0x0004
#define P6_PIO 0x00EC
#define P6_DIR 0x00EE
#define P6_PIN 0x00EC
#define P6_PEN 0x0010
#define P7_PIO 0xFFFF
#define P7_DIR 0xFFFF
#define P7_PIN 0xFFFF
#define P7_PEN 0x0000
#define P8_PIO 0x00F0
#define P8_DIR 0x00F2
#define P8_PIN 0x00F0
#define P8_PEN 0x0001
#define P9_PIO 0xFFFF
#define P9_DIR 0xFFFF
#define P9_PIN 0xFFFF
#define P9_PEN 0x0000
#define PC_PIO 0xFFFF
#define PC_DIR 0xFFFF
#define PC_PIN 0xFFFF
#define PC_PEN 0x0000
#define PORT_0 0
#define PORT_1 8
#define PORT_2 16
#define PORT_3 24
#define PORT_4 32
#define PORT_5 40
#define PORT_6 48
#define PORT_8 56
#define PUR_0123 0x01E0
#define PUR_4567 0x01E1
#define PUR_89 0x01E2
#define HAVE_SLEEP 1
#define HAVE_SLEEPnn 2
#define PWMC 1
#define PWMD 1
#define UART0X 1
#define UART0_PORT PORT_1
#define UART0_RXD_PIN 5
#define UART0_TXD_PIN 4
#define UART2X 1
#define UART2_PORT PORT_6
#define UART2_RXD_PIN 4
#define UART2_TXD_PIN 3
#define EXTINT0Y 1
#define EINT0_PORT PORT_4
#define EINT0_PIN 5
#define EXTINT1Y 1
#define EINT1_PORT PORT_1
#define EINT1_PIN 7
#define SPI0 1
#define HAVE_SPI0 0
#define SPI0_PORT PORT_3
#define SPI0_SS_PIN 3
#define SPI0_SCK_PIN 5
#define SPI0_SI_PIN 4
#define SPI0_SO_PIN 7
#define ADC 1
#define ADC_CH0_PORT PORT_0
#define ADC_CH0_PIN 7
#define ADC_CH0_NUM 0x00
#define ADC_CH0_REG AD0
#define ADC_CH1_PORT PORT_0
#define ADC_CH1_PIN 6
#define ADC_CH1_NUM 0x01
#define ADC_CH1_REG AD1
#define ADC_CH2_PORT PORT_0
#define ADC_CH2_PIN 5
#define ADC_CH2_NUM 0x02
#define ADC_CH2_REG AD2
#define ADC_CH3_PORT PORT_0
#define ADC_CH3_PIN 4
#define ADC_CH3_NUM 0x03
#define ADC_CH3_REG AD3
#define ADC_CH4_PORT PORT_0
#define ADC_CH4_PIN 3
#define ADC_CH4_NUM 0x04
#define ADC_CH4_REG AD4
#define ADC_CH5_PORT PORT_0
#define ADC_CH5_PIN 2
#define ADC_CH5_NUM 0x05
#define ADC_CH5_REG AD5
#define ADC_CH6_PORT PORT_0
#define ADC_CH6_PIN 1
#define ADC_CH6_NUM 0x06
#define ADC_CH6_REG AD6
#define ADC_CH7_PORT PORT_0
#define ADC_CH7_PIN 0
#define ADC_CH7_NUM 0x07
#define ADC_CH7_REG AD7
#define CLOCKSYS2 1
#define CLOCK_I_4 0x0400
#define CLOCK_I_8 0x0800
#define CLOCK_I_16 0x1000
#define CLOCK_I_20 0x1400
#define CLOCK_8_4 0x0408
#define CLOCK_8_8 0x0808
#define CLOCK_8_16 0x1008
#define CLOCK_8_32 0x2008
#define CLOCK_16_4 0x0410
#define CLOCK_16_8 0x0810
#define CLOCK_16_16 0x1010
#define CLOCK_16_32 0x2010
#define HAVE_I2C 1
#define I2C_TYPE 3
#define I2C_PORT 3
#define I2C_SCL_PIN 5
#define I2C_SDA_PIN 7
#define HAVE_TICKX 1
#define EESIZE 341
#define DFLASH_SIZE 4096
#define DFLASH_HALF_SIZE 2048
#define CANTYPE 36
#define CAN_PORT PORT_6
#define CAN_RXPIN 2
#define CAN_TXPIN 1
#define DFLASH 1
#define FASTMUL16 1
#define RAMSIZE 10240
#define UNILIB_PAUSE_MS 71
typedef int PORT_TYPE;
typedef unsigned char PORT_SIZE_TYPE;