LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity KOMPARATOR_1_BIT is
	port
	(
		E  : in  std_logic;
		A  : in  std_logic;
		B  : in  std_logic;
		Z0 : out std_logic;
		Z1 : out std_logic;
		Z2 : out std_logic
	);
end entity KOMPARATOR_1_BIT ;

architecture VERGLEICHER of KOMPARATOR_1_BIT is

begin
	Z2 <= E AND A AND (NOT (B) );
	Z1 <= ( E AND ( NOT (A)) AND (NOT (B))) OR  ( E AND A AND B );
	Z0 <= E AND (NOT (A) AND B);

end VERGLEICHER ;