LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity KOMPARATOR_4_BIT is
	port
	(
		X        : in  std_logic_vector(3 downto 0);
		Y        : in  std_logic_vector(3 downto 0);
		GROESSER : out std_logic;
		KLEINER  : out std_logic;
		GLEICH   : out std_logic
	);
end entity KOMPARATOR_4_BIT ;

architecture VERGLEICHER of KOMPARATOR_4_BIT is

	component KOMPARATOR_1_BIT is
		port
		(
			E  : in  std_logic;
			A  : in  std_logic;
			B  : in  std_logic;
			Z0 : out std_logic;
			Z1 : out std_logic;
			Z2 : out std_logic
		);
	end component;

	signal CARRY  : std_logic_vector(4 downto 0) := "10000";
	signal Z2_out : std_logic_vector(3 downto 0) := (others => '0');
	signal Z0_out : std_logic_vector(3 downto 0) := (others => '0');

begin

	GEN_KOMPARATOR_4_BIT : for i in 3 downto 0 generate

		inst_KOMPARATOR_1_BIT : KOMPARATOR_1_BIT
			port map
			(
				E  => CARRY(i + 1),
				A  => X(i),
				B  => Y(i),
				Z0 => Z0_out(i),
				Z1 => CARRY(i),
				Z2 => Z2_out(i)
			);

	end generate;

	GROESSER <= or Z2_out; -- VHDL2008 kann das!
	KLEINER  <= or Z0_out;
	GLEICH   <= CARRY(0);

end;