library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_komparator_4_bit is
end entity tb_komparator_4_bit ;

architecture tb of tb_komparator_4_bit is


	signal s_X        : std_logic_vector(3 downto 0) := (others => '0');
	signal s_Y        : std_logic_vector(3 downto 0) := (others => '0');
	signal s_GROESSER : std_logic := '0';
	signal s_KLEINER  : std_logic := '0';
	signal s_GLEICH   : std_logic := '0';
	
	signal s_lfsr     : std_logic_vector(31 downto 0) := x"01234567";

begin

	process
	begin
		for i in 0 to 1023 loop

			s_lfsr <= s_lfsr(30 downto 0) & not(s_lfsr(31) xor s_lfsr(22) xor s_lfsr(2) xor s_lfsr(1));
			s_X    <= s_lfsr(7 downto 4);
			s_Y    <= s_lfsr(19 downto 16);

			wait for 1 ns;
			
			if unsigned(s_X) > unsigned(s_Y) then
				if s_GROESSER = '0' or s_KLEINER = '1' or s_GLEICH = '1' then
					report "Fehler" severity error;
				end if;
			elsif unsigned(s_X) < unsigned(s_Y) then
				if s_GROESSER = '1' or s_KLEINER = '0' or s_GLEICH = '1' then
					report "Fehler" severity error;
				end if;
			else
				if s_GROESSER = '1' or s_KLEINER = '1' or s_GLEICH = '0' then
					report "Fehler" severity error;
				end if;
			end if;

			wait for 1 ns;

		end loop;
		wait;
	end process;

	inst_KOMPARATOR_4_BIT : entity work.KOMPARATOR_4_BIT
		port map
		(
			X        => s_X,
			Y        => s_Y,
			GROESSER => s_GROESSER,
			KLEINER  => s_KLEINER,
			GLEICH   => s_GLEICH
		);

end;