library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity tb_WAS_MACH_ICH is
end entity tb_WAS_MACH_ICH;

architecture tb of tb_WAS_MACH_ICH is

	signal AUSWAHL : std_logic_vector(2 downto 0) := "000";
	signal LEDR : std_logic_vector(5 downto 0) := (others => '0');
	
begin
	
	process
	begin
		wait for 1 ns;
		AUSWAHL <= std_logic_vector(unsigned(AUSWAHL) + 1);
	end process;
	
	inst_WAS_MACH_ICH : entity work.WAS_MACH_ICH
		port map
		(
			AUSWAHL => AUSWAHL,
			LEDR    => LEDR
		);

end;