library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity poly_mult is
end poly_mult;

architecture tb of poly_mult is

	signal S_INP                       : std_logic_vector(0 to 11) := "110100000000";

	signal clk                         : std_logic := '0';
	signal inp                         : std_logic := '0';
	signal r                           : std_logic_vector(7 downto 0) := (others => '0');
	signal out_2                       : std_logic := '0';
	
	signal S_OUT                       : std_logic_vector(0 to 11) := (others => '0');

begin

	clk <= not clk after 5 ns;
	
	inp <= S_INP(0);
	out_2 <= r(7) xor inp;
	
	process
	begin
		wait until rising_edge(clk);
			S_INP <= S_INP(1 to 11) & '0';
			r(0)  <= inp;
			r(1)  <= r(0) xor inp;
			r(2)  <= r(1) xor inp;
			r(3)  <= r(2);
			r(4)  <= r(3) xor inp;
			r(5)  <= r(4);
			r(6)  <= r(5);
			r(7)  <= r(6) xor inp;
			S_OUT <= S_OUT(1 to 11) & out_2;
	end process;

end;