library IEEE;
use IEEE.std_logic_1164.all;

entity Debounce_Test is
    port
	(
        BTN : in  std_logic;
        LED : out std_logic_vector(7 downto 0) := (others => '0')
    );
end entity Debounce_Test;

architecture rtl of Debounce_Test is

	signal s_led_sr : std_logic_vector(7 downto 0) := x"01";

begin
    process
    begin
		wait until rising_edge(BTN);
		s_led_sr <= s_led_sr(6 downto 0) & s_led_sr(7);
    end process;
	
    LED <= s_led_sr;
	
end;