library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity Debounce_Test_max10 is
	port
	(
		-- -- CLOCK
		-- i_clk_25                       : in    std_logic;
		-- -- UART
		-- i_uart_rx                      : in    std_logic;
		-- o_uart_tx                      : out   std_logic;
		-- -- ADC
		-- o_adc_cnv                      : out   std_logic;
		-- o_adc_sck                      : out   std_logic;
		-- o_adc_mosi                     : out   std_logic;
		-- i_adc_miso                     : in    std_logic;
		-- -- ACCEL
		-- o_accel_scl                    : out   std_logic;
		-- io_accel_sda                   : inout std_logic;
		-- -- SR
		-- o_sr_ser                       : out   std_logic;
		-- o_sr_srclk                     : out   std_logic;
		-- o_sr_rclk                      : out   std_logic;
		-- BTN
		BTN                            : in    std_logic;
		-- LED
		-- o_led                          : out   std_logic;
		-- PMOD
		LED                            : out   std_logic_vector(7 downto 0)
	);
end Debounce_Test_max10;

architecture rtl of Debounce_Test_max10 is

    signal counter : integer := 0;
	signal s_led   : std_logic_vector(7 downto 0) := x"00";

begin

    process
    begin
        wait until rising_edge(BTN);
        counter <= counter + 1;
    end process;
	s_led(counter) <= '1';
    LED <= s_led;

end architecture rtl;