--Copyright 2022, Lutz Locus
--for educational purposes only
library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Debounce_Test is
  port(
    BTN_i : in std_logic;
    LED_o : out std_logic_vector(7 downto 0));
end entity Debounce_Test;

architecture rtl of Debounce_Test is
  signal shift_reg_q  : std_logic_vector(7 downto 0):= (others => '0');
  signal first_done_q : std_logic := '0';
begin

  process(BTN_i)
  begin
    if rising_edge(BTN_i) then
      if first_done_q = '0' then
        first_done_q   <= '1';
        shift_reg_q(0) <= '1';
      else
        shift_reg_q <= shift_reg_q(6 downto 0) & shift_reg_q(7);
      end if;
    end if;
  end process;

  LED_o <= shift_reg_q;

end architecture rtl;