--Copyright 2022, Lutz Locus
--Verion 20221219a
--for educational purposes only
--synchronous to clk_i design with synchronous reset,
--not using register initialization (as in xilinx)
--
--target: FPGA-design (not PLD) Xilinx prefered, Altera (others will do also)


--after Power up all bits in led_o are zero
--with first rising edge at btn_1 a single '1' is set at (0)
--with further rising edges at btn_1 the '1' is shown on the next (index+1) position ("Running '1'")
--                                   --when at position (7) the bit will be set at Position (0) (rotating)

library IEEE;

use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;

entity Debounce_Test is
  port(
    clk_i  : in  std_logic;
    rst_ni : in  std_logic;
    --
    btn_i  : in  std_logic;
    led_o  : out std_logic_vector(7 downto 0));
end entity Debounce_Test;

architecture rtl of Debounce_Test is

  signal first_done_q : std_logic;
  signal btn_del_q    : std_logic;

  subtype T_CNT is integer range 0 to 7;
  signal bit_cnt_q : T_CNT;
begin

  process(clk_i)
  begin
    if rising_edge(clk_i) then
      if rst_ni = '0' then                       --sync reset
        first_done_q <= '0';
        btn_del_q    <= '0';
        bit_cnt_q    <= T_CNT'low;
      else
        btn_del_q <= btn_i;                      --for edge detection
        --
        if btn_del_q = '0' and btn_i = '1' then  --rising edge button
          if first_done_q = '0' then             --not started yet? 
            first_done_q <= '1';
          else
            if bit_cnt_q = T_CNT'high then       --bit count overflow?
              bit_cnt_q <= T_CNT'low;
            else
              bit_cnt_q <= bit_cnt_q + 1;        --count
            end if;
          end if;  --first_done_q
        end if;  --button 
      end if;  --rst_n
    end if;  --clk
  end process;

  --combinatorical process for 1-out-of-8 encodung outputs
  --this drives the output led_o directly (no FF-buffering)
  process(bit_cnt_q, first_done_q)
    if first_done_q = '0' then
      LED_o(index) <= (others => '0');
    else
      for index in 0 to 7 loop
        if index = bit_cnt_q then
          LED_o(index) <= '1';
        else
          LED_o(index) <= '0';
        end if;
      end loop;
    end if;
  end process;

end architecture rtl;