-- Quartus Prime VHDL Template
-- Binary Counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pulse_counter is

	generic
	(
		MIN_COUNT : natural := 0;
		MAX_COUNT : natural := 512
	);

	port
	(
		clk		  : in std_logic;
		reset	  : in std_logic;
		A	  : in std_logic;
		B	  : in std_logic;
		index	: in std_logic;
		A_out	  : out std_logic;
		B_out	  : out std_logic;
		index_out	: out std_logic;
		count		  : out std_logic_vector(15 downto 0)
	);

end entity;

architecture Behavioral of pulse_counter is


Signal Zustand : std_logic_vector(1 downto 0);
Signal A_old : std_logic;
Signal B_old : std_logic;
Signal Zustand_old : std_logic_vector(1 downto 0);
signal index_old : std_logic;



begin

	process (clk)
		variable   cnt		   : std_logic_vector (15 downto 0);
		variable   overflow		   : integer range MIN_COUNT to MAX_COUNT;
		
	begin
		if (rising_edge(clk)) then

			if reset = '1' then
		
			overflow := 0;
					

			else
			

				if A = '1' and A_old = '0' and B = '0' then
					Zustand <= "00";
												--Pos 0
				end if;
				if A = '1' and B = '1' and B_old = '0' then
					Zustand <= "01";
												--Pos 1
			   end if;
				if A = '0' and A_old = '1' and B = '1' then
					Zustand <= "10";
												--Pos 2 
			   end if;
				if A = '0' and B = '0' and B_old = '1' then
					Zustand <= "11";
												--Pos 3
			   end if;
				if Zustand = "00" and Zustand_old = "11" and index = '1' and index_old = '0'  then
					overflow := overflow + 1;
				elsif Zustand = "11" and Zustand_old = "00" and index = '1' and index_old = '0'  then
					overflow := overflow - 1;
			   end if;
			
			A_old <= A ;
			B_old <= b ;
			index_old <= index; 
			Zustand_old <= Zustand;
				
			
		   end if;
			
			-- Output the current count
			count(1 downto 0) <= Zustand;
			count(15 downto 2) <= std_logic_vector(to_unsigned(overflow,14));
		

		end if;
	end process;

end behavioral;