#include #include #include #include #define TXLED BIT0 #define RXLED BIT1 #define TXD BIT0 #define RXD BIT1 int main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer // Configure one FRAM waitstate as required by the device datasheet for MCLK // operation beyond 8MHz _before_ configuring the clock system. FRCTL0 = FRCTLPW | NWAITS_1; // Clock System Setup CSCTL0_H = CSKEY_H; // Unlock CS registers CSCTL1 = DCOFSEL_0; // Set DCO to 1MHz CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK; // Set SMCLK = MCLK = DCO, ACLK = VLOCLK // Per Device Errata set divider to 4 before changing frequency to // prevent out of spec operation from overshoot transient CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4; // Set all corresponding clk sources to divide by 4 for errata CSCTL1 = DCOFSEL_4 | DCORSEL; // Set DCO to 16MHz // Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz)) __delay_cycles(60); CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers to 1 for 16MHz operation CSCTL0_H = 0; // Lock CS registers // Init UART UCA0CTL1 = UCSWRST; // Stop UART UCA0BR0 = 104; // 9600bps @16MHz UCA0BR1 = 2; // 9600bps @16MHz UCA0MCTLW = 0x49; // 9600bps @16MHz UCA0CTL1 = UCSSEL__SMCLK; // Start UART, connect it to SMCLK // Init Pins PM5CTL0 &= ~LOCKLPM5; // Enable ports P2SEL0 |= TXD | RXD; // Set tertiary pin function on UART pins P2SEL1 |= TXD | RXD; // set tertiary pin function on uart pins P1DIR |= BIT0; // Configure P1.0 as output (LED) P1OUT |= BIT0; // Set P1.0 (LED on) __delay_cycles(16e6); // Delay about a second P1OUT &= ~BIT0; // Clear P1.0 (LED off) while (true) { __delay_cycles(16e5); // Delay about 0.1s P1OUT |= BIT0; // Set P1.0 (LED on) while (!(UCA0IFG & UCTXCPTIFG)) ; // Check if TX is ready __delay_cycles(16e5); // Delay about 0.1s P1OUT &= ~BIT0; // Clear P1.0 (LED off) UCA0TXBUF = 'x'; // Transmit an 'x' } }