library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SekundenZaehler7Segment is
  port(
    clk         : in  std_logic;
    reset       : in  std_logic;
    segments_1  : out std_logic_vector(6 downto 0);
    segments_10 : out std_logic_vector(6 downto 0));
end SekundenZaehler7Segment;

architecture rtl of SekundenZaehler7Segment is
  signal clk_en           : std_logic;
  signal counter_1        : std_logic_vector(3 downto 0);
  signal counter_10       : std_logic_vector(3 downto 0);
  signal overflow_1       : std_logic;
  signal overflow_10      : std_logic;
  signal segments_1_temp  : std_logic_vector(6 downto 0);
  signal segments_10_temp : std_logic_vector(6 downto 0);

  component ClockEnableGenerator is
    generic (
      DIVIDE_BY : integer);
    port(
      clk_in     : in  std_logic;
      clk_en_out : out std_logic;
      reset      : in  std_logic);
  end component;

  component GenericBCDCounter is
    generic (COUNT_MAX : integer);
    port(
      clk      : in  std_logic;
      enable   : in  std_logic;
      reset    : in  std_logic;
      count    : out std_logic_vector(3 downto 0);
      overflow : out std_logic);
  end component;

  component BCDDecoder is
    port(
      digit    : in  std_logic_vector(3 downto 0);
      segments : out std_logic_vector(6 downto 0));
  end component;

begin
  Decoder1 : BCDDecoder
    port map (
      digit    => counter_1,
      segments => segments_1_temp);

  Decoder10 : BCDDecoder
    port map (
      digit    => counter_10,
      segments => segments_10_temp);

  Counter1 : GenericBCDCounter
    generic map (COUNT_MAX => 9)
    port map (
      clk      => clk,
      enable   => clk_en,
      reset    => reset,
      count    => counter_1,
      overflow => overflow_1);

  Counter10 : GenericBCDCounter
    generic map (COUNT_MAX => 5)
    port map (
      clk      => clk,
      enable   => overflow_1,
      reset    => reset,
      count    => counter_10,
      overflow => overflow_10);

  ClockGen : ClockEnableGenerator
    generic map (DIVIDE_BY => 13)
     port map (
      clk_in     => clk,
      clk_en_out => clk_en,
      reset      => reset);

  segments_1 <= segments_1_temp;
  segments_10 <= segments_10_temp;

end architecture rtl;