LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY tb_berlinuhr IS
END tb_berlinuhr;
 
ARCHITECTURE behavior OF tb_berlinuhr IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT berlinuhr
    PORT(
         clk32k : IN  std_logic;
         setslow : IN  std_logic;
         setfast : IN  std_logic;
         sec : OUT  std_logic;
         min : BUFFER  std_logic_vector(3 downto 0);
         min5 : BUFFER  std_logic_vector(10 downto 0);
         hr : BUFFER  std_logic_vector(3 downto 0);
         hr5 : BUFFER  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk32k : std_logic := '0';
   signal setslow : std_logic := '0';
   signal setfast : std_logic := '0';

 	--Outputs
   signal sec : std_logic;
   signal min : std_logic_vector(3 downto 0);
   signal min5 : std_logic_vector(10 downto 0);
   signal hr : std_logic_vector(3 downto 0);
   signal hr5 : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk32k_period : time := 30517 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: berlinuhr PORT MAP (
          clk32k => clk32k,
          setslow => setslow,
          setfast => setfast,
          sec => sec,
          min => min,
          min5 => min5,
          hr => hr,
          hr5 => hr5
        );

   -- Clock definitions
   clk32k <= not clk32k after clk32k_period/2;
 

   set_test: process
   begin		
      wait for 100000 ms;	
      setfast <= '1';
      wait for 100000 ms;
      setfast <= '0';
      wait for 100000 ms;	
      setslow <= '1';
      wait for 100000 ms;
      setslow <= '0';
      wait;
   end process;


END;