PROPERTY
ATMEL...

Cascade_Logic
fast_inlatch
Foldback_Logic
GCK_ITD
Global_Fold
Global_OE
JTAG
Latch_Synthesis
logic_doubling
MC_power
OE_node
open_collector
Optimize
Out_Edif
output_fast
pin_keep
power_reset
preassign
Push_Gate
security
Soft_Buffer
TDI_pullup
TMS_pullup
twoclock
Verilog_sim
Vhdl_sim
XOR_Synthesis


APPEND
ASSEMBLY
ASSY
COMPANY
CONDITION
DATE
DEFAULT
DESIGNER
DEVICE
ELSE
FIELD
FLD
FORMAT
FUNCTION
FUSE
GROUP
IF
JUMP
LOC
LOCATION
MACRO
MIN
NAME
NEXT
NODE
ORDER
OUT
PARTNO
PIN
PINNODE
PRESENT
REV
REVISION
SEQUENCE
SEQUENCED
SEQUENCEJK
SEQUENCERS
SEQUENCET
TABLE
VECTORS

CUPL operators:
'h' 'b' 'd' $ & # ! == { } [ ]