// registers for flash control
reg [7:0]  r_flash_status;
reg [15:0] r_flash_ctrl;
reg        r_flash_ctrl_wr;
reg [16:0] r_flash_addr;
reg        r_flash_write;
reg        r_flash_autoinc;
reg [31:0] r_flash_data_in;
reg [31:0] r_flash_data_out;
reg        r_flash_data_wr;
reg        r_reconfig;

// internal signals
reg [7:0] regmem [0:31]; // register block 
reg [7:0] regread;
reg [7:0] bus_value;
reg [15:0] bus_ttl;

// writing registers 
integer i; // for loop index used for reset of all registers
always @(posedge clkb or negedge rstb)
begin
	if (~rstb) begin // reset condition
		for (i=0;i<27;i=i+1) regmem[i] <= 8'h00; // do not reset registers 27...31
		bus_value <= 8'd0;
		bus_ttl   <= 16'd0;
		
		// reset flash control registers
		r_flash_addr <= 17'd0;
        r_flash_ctrl <= 16'hFFFF;
        r_flash_data_out <= 32'd0;
        r_flash_write <= 1'd0;
        r_flash_autoinc <= 1'd0;
        r_flash_ctrl_wr <= 1'b0;
        r_flash_data_wr <= 1'b0;
        r_reconfig <= 1'b0;
	end 
	else begin
        i=0; // fix warning
        // when signals are valid write into register memory
        if (ienb) begin
            if (flashen & mainreg) begin
                if (~cs) begin
                    if (~rw) begin
                        case (addr)
                            5'h01: begin 
                                r_flash_ctrl[7:0] <= i_data;
                                r_flash_ctrl[15:8] <= r_flash_ctrl[15:8] | 8'b00000111;
                                r_flash_ctrl_wr <= r_flash_write;
                            end
                            5'h02: begin 
                                r_flash_ctrl[15:8] <= i_data;
                                r_flash_ctrl[7:0] <= r_flash_ctrl[7:0] | {8{&i_data[2:0]}};
                                r_flash_ctrl_wr <= r_flash_write;
                            end
                            5'h03: r_flash_addr[7:0] <= i_data;
                            5'h04: r_flash_addr[15:8] <= i_data;
                            5'h05: begin
                                r_flash_write <= (~r_flash_write & i_data[7]) ? ({i_data,r_flash_addr[15:0]} == `WRITEPROTECTVALUE) : i_data[7];
                                r_flash_autoinc <= i_data[6];
                                r_flash_addr[16] <= i_data[0];
                            end
                            5'h06: r_flash_data_out[7:0] <= i_data;
                            5'h07: r_flash_data_out[15:8] <= i_data;
                            5'h08: r_flash_data_out[23:16] <= i_data;
                            5'h09: begin
                                r_flash_data_out[31:24] <= i_data;
                                r_flash_data_wr <= r_flash_write;
                            end
                            5'h0d: r_reconfig <= i_data[0];
                            5'h19: regmem[addr] <= i_data;
                            5'h1A: regmem[addr] <= i_data;
                            default: ; // nothing
                        endcase
                    end
                    else begin // read condition
                        r_flash_ctrl_wr <= 1'b0;
                        r_flash_data_wr <= 1'b0;
                        if (addr == 5'h09) begin // read from data[31:24] triggers autoinc
                            r_flash_addr <= (~r_flash_write & r_flash_autoinc) ? r_flash_addr + 17'd1 : r_flash_addr;
                        end
                    end
                end
                else begin
                    r_flash_ctrl_wr <= 1'b0;
                    r_flash_data_wr <= 1'b0;
                    if (r_flash_data_wr) begin // in case something had been written in the last cycle
                        r_flash_addr <= (r_flash_write & r_flash_autoinc) ? r_flash_addr + 17'd1 : r_flash_addr; 
                    end
                end
            end
            
            // standard write with bitrot
            else if ( (noextra | magicen)
                    & ( ~(rw|cs))       ) 
            begin
    	       regmem[addr] <= i_data; // write condition
    	       bus_value    <= i_data;
    	       bus_ttl      <= conf[4] ? `BITROT8580 : `BITROT6581; // well, these values are just values...
            end 
            else begin 
                if (|bus_ttl) begin
                    bus_ttl     <= bus_ttl - 16'd1;
                    bus_value   <= bus_value &
                                   ( {8{|bus_ttl[15:7]}} // high up to the last 128 samples 
                                   | {bus_ttl[4],bus_ttl[2],bus_ttl[6]|bus_ttl[5],bus_ttl[1],bus_ttl[6],bus_ttl[3],bus_ttl[7]|bus_ttl[6],bus_ttl[0]}); 
                                   // above we fade out the last 128 values in a weired but very predictable pattern
                end
                else begin
                    // bitrot done 
                    bus_value   <= 8'd0;
                    bus_ttl     <= 16'd0;
                end
            end
    	end
        // update configuration change when nothing else happens
        else if (config_write) begin 
            regmem[27] <= 8'h00;
            regmem[28][7:4] <= 4'h0; // upper 4 bits of bias are zero
            regmem[28][3:0] <= config_reg[configselect_current][3:0];
            regmem[29] <= config_reg[configselect_current][15:8];
            regmem[30] <= config_reg[configselect_current][23:16];
            regmem[31] <= config_reg[configselect_current][31:24];
        end 
    end
end
assign configselect_current = {~configselect_d,mainreg[0]};