library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LCD16x2TEST is
    Port ( clk_50M : in  STD_LOGIC;
           LCD_DB  : out  STD_LOGIC_VECTOR (7 downto 0);
           LCD_E   : out  STD_LOGIC;
           LCD_RW  : out STD_LOGIC;
           LCD_RS  : out  STD_LOGIC
    );
end LCD16x2TEST;

architecture Behavioral of LCD16x2TEST is
component CHAR_LCD_CTR is
    Port ( clk_50M            : in  STD_LOGIC;
           LCDData            : out  STD_LOGIC_VECTOR (7 downto 0);
           LCD_Enable         : out  STD_LOGIC;
           LCD_RW             : out STD_LOGIC;
           LCD_RegisterSelect : out  STD_LOGIC;
           init_done          : out std_logic;
           address            : in std_logic_vector(4 downto 0);
           data               : in std_logic_vector(7 downto 0);
           wr                 : in std_logic
    );
end component;
signal init_done  : std_logic;
signal address    : std_logic_vector(4 downto 0) := (others =>'0');
signal data       : std_logic_vector(7 downto 0) := x"23";
signal wr         : std_logic := '0';
constant end_Addr : integer := 15;
begin

    TEST: process 
    begin
    wait until rising_edge(clk_50m);    
        if init_done = '1' then
            wr      <= '1';
            if address /= end_Addr then
                address <= address + 1;
            else
                address <= (others => '0');
            end if;
        end if;
    end process;

LCD16x2: CHAR_LCD_CTR 
    Port map(clk_50M, LCD_DB, LCD_E, LCD_RW, LCD_RS, init_done, address, data, wr);
end Behavioral;