library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ClockEnableGenerator is
	generic
	(
		DIVIDE_BY : integer
	);
	port
	(
		clk_in     : in  std_logic;
		clk_en_out : out std_logic;
		reset      : in  std_logic
	);
end ClockEnableGenerator;

architecture rtl of ClockEnableGenerator is

	signal counter : integer range 0 to DIVIDE_BY - 1 := 0;

begin

	process (reset, clk_in)
	begin
		if reset = '1' then
			counter <= 0;
			clk_en_out <= '0';
		else
			if rising_edge(clk_in) then
				clk_en_out <= '0';
				if counter = DIVIDE_BY - 1 then
					clk_en_out <= '1';
					counter <= 0;
				else
					counter <= counter + 1;
				end if;
			end if;
		end if;
	end process;

end;