library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity GenericBCDCounter is
	generic
	(
		COUNT_MAX : integer
	);
	port
	(
		clk      : in  std_logic;
		enable   : in  std_logic;
		reset    : in  std_logic;
		count    : out std_logic_vector(3 downto 0);
		overflow : out std_logic
	);
end GenericBCDCounter;

architecture rtl of GenericBCDCounter is

	signal counter : integer range 0 to COUNT_MAX := 0;

begin

	count <= std_logic_vector(to_unsigned(counter, 4));

	process (reset, clk)
	begin
		if reset = '1' then
			counter <= 0;
			overflow <= '0';
		else
			if rising_edge(clk) then
				overflow <= '0';
				if enable = '1' then
					if counter = COUNT_MAX then
						counter <= 0;
						overflow <= '1';
					else
						counter <= counter + 1;
					end if;
				end if;
			end if;
		end if;
	end process;

end;