Equations

$OpTx$FX_DC$1 <= AVR_AH(0)
      XOR
     $OpTx$FX_DC$1 <= AVR_AH(1);
AVR_AD_I(0) <= ((NOT AVR_AH(0) AND SPI_CS(0).PIN)
      OR (AVR_AH(1) AND SPI_CS(0).PIN)
      OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(0)));
     AVR_AD(0) <= AVR_AD_I(0) when AVR_AD_OE(0) = '1' else 'Z';
     AVR_AD_OE(0) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1);
AVR_AD_I(1) <= ((NOT AVR_AH(0) AND SPI_CS(1).PIN)
      OR (AVR_AH(1) AND SPI_CS(1).PIN)
      OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(1)));
     AVR_AD(1) <= AVR_AD_I(1) when AVR_AD_OE(1) = '1' else 'Z';
     AVR_AD_OE(1) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1);
AVR_AD_I(2) <= ((NOT AVR_AH(0) AND SPI_CS(2).PIN)
      OR (AVR_AH(1) AND SPI_CS(2).PIN)
      OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(2)));
     AVR_AD(2) <= AVR_AD_I(2) when AVR_AD_OE(2) = '1' else 'Z';
     AVR_AD_OE(2) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1);
AVR_AD_I(3) <= ((NOT AVR_AH(0) AND SPI_CS(3).PIN)
      OR (AVR_AH(1) AND SPI_CS(3).PIN)
      OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(3)));
     AVR_AD(3) <= AVR_AD_I(3) when AVR_AD_OE(3) = '1' else 'Z';
     AVR_AD_OE(3) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1);
AVR_AD_I(4) <= ((NOT AVR_AH(0) AND SPI_CS(4).PIN)
      OR (AVR_AH(1) AND SPI_CS(4).PIN)
      OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(4)));
     AVR_AD(4) <= AVR_AD_I(4) when AVR_AD_OE(4) = '1' else 'Z';
     AVR_AD_OE(4) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1);
AVR_AD_I(5) <= ((NOT AVR_AH(0) AND SPI_CS(5).PIN)
      OR (AVR_AH(1) AND SPI_CS(5).PIN)
      OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(5)));
     AVR_AD(5) <= AVR_AD_I(5) when AVR_AD_OE(5) = '1' else 'Z';
     AVR_AD_OE(5) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1);
AVR_AD_I(6) <= ((NOT AVR_AH(0) AND SPI_CS(6).PIN)
      OR (AVR_AH(1) AND SPI_CS(6).PIN)
      OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(6)));
     AVR_AD(6) <= AVR_AD_I(6) when AVR_AD_OE(6) = '1' else 'Z';
     AVR_AD_OE(6) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1);
AVR_AD_I(7) <= ((NOT AVR_AH(0) AND SPI_CS(7).PIN)
      OR (AVR_AH(1) AND SPI_CS(7).PIN)
      OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(7)));
     AVR_AD(7) <= AVR_AD_I(7) when AVR_AD_OE(7) = '1' else 'Z';
     AVR_AD_OE(7) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1);
FDCPE_Bank_Reg0: FDCPE port map (Bank_Reg(0),'0','0',Bank_Reg_CLR(0),Bank_Reg_PRE(0));
     Bank_Reg_CLR(0) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      NOT AVR_AD(0).PIN AND NOT AVR_WR);
     Bank_Reg_PRE(0) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      AVR_AD(0).PIN AND NOT AVR_WR);
FDCPE_Bank_Reg1: FDCPE port map (Bank_Reg(1),'0','0',Bank_Reg_CLR(1),Bank_Reg_PRE(1));
     Bank_Reg_CLR(1) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      NOT AVR_AD(1).PIN AND NOT AVR_WR);
     Bank_Reg_PRE(1) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      AVR_AD(1).PIN AND NOT AVR_WR);
FDCPE_Bank_Reg2: FDCPE port map (Bank_Reg(2),'0','0',Bank_Reg_CLR(2),Bank_Reg_PRE(2));
     Bank_Reg_CLR(2) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      NOT AVR_AD(2).PIN AND NOT AVR_WR);
     Bank_Reg_PRE(2) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      AVR_AD(2).PIN AND NOT AVR_WR);
FDCPE_Bank_Reg3: FDCPE port map (Bank_Reg(3),'0','0',Bank_Reg_CLR(3),Bank_Reg_PRE(3));
     Bank_Reg_CLR(3) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      NOT AVR_AD(3).PIN AND NOT AVR_WR);
     Bank_Reg_PRE(3) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      AVR_AD(3).PIN AND NOT AVR_WR);
FDCPE_Bank_Reg4: FDCPE port map (Bank_Reg(4),'0','0',Bank_Reg_CLR(4),Bank_Reg_PRE(4));
     Bank_Reg_CLR(4) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      NOT AVR_AD(4).PIN AND NOT AVR_WR);
     Bank_Reg_PRE(4) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      AVR_AD(4).PIN AND NOT AVR_WR);
FDCPE_Bank_Reg5: FDCPE port map (Bank_Reg(5),'0','0',Bank_Reg_CLR(5),Bank_Reg_PRE(5));
     Bank_Reg_CLR(5) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      NOT AVR_AD(5).PIN AND NOT AVR_WR);
     Bank_Reg_PRE(5) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      AVR_AD(5).PIN AND NOT AVR_WR);
FDCPE_Bank_Reg6: FDCPE port map (Bank_Reg(6),'0','0',Bank_Reg_CLR(6),Bank_Reg_PRE(6));
     Bank_Reg_CLR(6) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      NOT AVR_AD(6).PIN AND NOT AVR_WR);
     Bank_Reg_PRE(6) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      AVR_AD(6).PIN AND NOT AVR_WR);
FDCPE_Bank_Reg7: FDCPE port map (Bank_Reg(7),'0','0',Bank_Reg_CLR(7),Bank_Reg_PRE(7));
     Bank_Reg_CLR(7) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      NOT AVR_AD(7).PIN AND NOT AVR_WR);
     Bank_Reg_PRE(7) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND
      AVR_AD(7).PIN AND NOT AVR_WR);
FTDI_RD <= NOT ((AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND
      NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND AVR_AH(1)));
FTDI_WR <= NOT ((AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND AVR_AH(1) AND NOT AVR_WR));
MMD_CS(0) <= NOT ((AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(0) AND NOT AVR_AH(1)));
MMD_CS(1) <= ((NOT AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5))
      OR (NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND
      NOT AVR_AH(2))
      OR (NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND
      NOT AVR_AH(0) AND NOT AVR_AH(1)));
FDCPE_SPI_CS0: FDCPE port map (SPI_CS(0),'0','0',SPI_CS_CLR(0),SPI_CS_PRE(0));
     SPI_CS_CLR(0) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      NOT AVR_AD(0).PIN AND NOT AVR_WR);
     SPI_CS_PRE(0) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      AVR_AD(0).PIN AND NOT AVR_WR);
FDCPE_SPI_CS1: FDCPE port map (SPI_CS(1),'0','0',SPI_CS_CLR(1),SPI_CS_PRE(1));
     SPI_CS_CLR(1) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      NOT AVR_AD(1).PIN AND NOT AVR_WR);
     SPI_CS_PRE(1) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      AVR_AD(1).PIN AND NOT AVR_WR);
FDCPE_SPI_CS2: FDCPE port map (SPI_CS(2),'0','0',SPI_CS_CLR(2),SPI_CS_PRE(2));
     SPI_CS_CLR(2) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      NOT AVR_AD(2).PIN AND NOT AVR_WR);
     SPI_CS_PRE(2) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      AVR_AD(2).PIN AND NOT AVR_WR);
FDCPE_SPI_CS3: FDCPE port map (SPI_CS(3),'0','0',SPI_CS_CLR(3),SPI_CS_PRE(3));
     SPI_CS_CLR(3) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      NOT AVR_AD(3).PIN AND NOT AVR_WR);
     SPI_CS_PRE(3) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      AVR_AD(3).PIN AND NOT AVR_WR);
FDCPE_SPI_CS4: FDCPE port map (SPI_CS(4),'0','0',SPI_CS_CLR(4),SPI_CS_PRE(4));
     SPI_CS_CLR(4) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      NOT AVR_AD(4).PIN AND NOT AVR_WR);
     SPI_CS_PRE(4) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      AVR_AD(4).PIN AND NOT AVR_WR);
FDCPE_SPI_CS5: FDCPE port map (SPI_CS(5),'0','0',SPI_CS_CLR(5),SPI_CS_PRE(5));
     SPI_CS_CLR(5) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      NOT AVR_AD(5).PIN AND NOT AVR_WR);
     SPI_CS_PRE(5) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      AVR_AD(5).PIN AND NOT AVR_WR);
FDCPE_SPI_CS6: FDCPE port map (SPI_CS(6),'0','0',SPI_CS_CLR(6),SPI_CS_PRE(6));
     SPI_CS_CLR(6) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      NOT AVR_AD(6).PIN AND NOT AVR_WR);
     SPI_CS_PRE(6) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      AVR_AD(6).PIN AND NOT AVR_WR);
FDCPE_SPI_CS7: FDCPE port map (SPI_CS(7),'0','0',SPI_CS_CLR(7),SPI_CS_PRE(7));
     SPI_CS_CLR(7) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      NOT AVR_AD(7).PIN AND NOT AVR_WR);
     SPI_CS_PRE(7) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND
      NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND
      AVR_AD(7).PIN AND NOT AVR_WR);
SRAM_AH(0) <= ((AVR_AH(7) AND Bank_Reg(4))
      OR (NOT AVR_AH(7) AND Bank_Reg(0)));
SRAM_AH(1) <= ((AVR_AH(7) AND Bank_Reg(5))
      OR (NOT AVR_AH(7) AND Bank_Reg(1)));
SRAM_AH(2) <= ((AVR_AH(7) AND Bank_Reg(6))
      OR (NOT AVR_AH(7) AND Bank_Reg(2)));
SRAM_AH(3) <= ((AVR_AH(7) AND Bank_Reg(7))
      OR (NOT AVR_AH(7) AND Bank_Reg(3)));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);