library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ToDownto is Port ( downto_vect_in : in STD_LOGIC_VECTOR (3 downto 0); to_vect_in : in STD_LOGIC_VECTOR (0 to 3); downto_vect_out : out STD_LOGIC_VECTOR (3 downto 0); to_vect_out : out STD_LOGIC_VECTOR (0 to 3); alias_to_vect_out : out STD_LOGIC_VECTOR (0 to 3); alias_downto_vect_out : out STD_LOGIC_VECTOR (0 to 3); bitwise_alias_downto_vect_out : out STD_LOGIC_VECTOR (3 downto 0); a0 : out STD_LOGIC; a1 : out STD_LOGIC; a2 : out STD_LOGIC; a3 : out STD_LOGIC; b0 : out STD_LOGIC; b1 : out STD_LOGIC; b2 : out STD_LOGIC; b3 : out STD_LOGIC); end ToDownto; architecture Behavioral of ToDownto is alias alias_to_vect: std_logic_vector(0 to 3) is downto_vect_in(3 downto 0); begin a0 <= downto_vect_in(0); a1 <= downto_vect_in(1); a2 <= downto_vect_in(2); a3 <= downto_vect_in(3); b0 <= to_vect_in(0); b1 <= to_vect_in(1); b2 <= to_vect_in(2); b3 <= to_vect_in(3); downto_vect_out <= to_vect_in; to_vect_out <= downto_vect_in; alias_to_vect_out <= alias_to_vect; alias_downto_vect_out <= alias_to_vect; bitwise_alias_downto_vect_out(0) <= alias_to_vect(0); bitwise_alias_downto_vect_out(1) <= alias_to_vect(1); bitwise_alias_downto_vect_out(2) <= alias_to_vect(2); bitwise_alias_downto_vect_out(3) <= alias_to_vect(3); end Behavioral;