Analysis & Synthesis report for Kap10_SiebensegmentVierstelligZaehler
Tue Nov 29 15:02:33 2022
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Parameter Settings for User Entity Instance: Top-level Entity: |Kap10_SiebensegmentVierstelligZaehler
 12. Parameter Settings for Inferred Entity Instance: lpm_divide:Mod0
 13. Parameter Settings for Inferred Entity Instance: lpm_divide:Div0
 14. Parameter Settings for Inferred Entity Instance: lpm_divide:Mod1
 15. Parameter Settings for Inferred Entity Instance: lpm_divide:Div1
 16. Parameter Settings for Inferred Entity Instance: lpm_divide:Mod2
 17. Parameter Settings for Inferred Entity Instance: lpm_divide:Div2
 18. Parameter Settings for Inferred Entity Instance: lpm_divide:Mod3
 19. Post-Synthesis Netlist Statistics for Top Partition
 20. Elapsed Time Per Partition
 21. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Nov 29 15:02:33 2022       ;
; Quartus Prime Version              ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
; Revision Name                      ; Kap10_SiebensegmentVierstelligZaehler       ;
; Top-level Entity Name              ; Kap10_SiebensegmentVierstelligZaehler       ;
; Family                             ; MAX 10                                      ;
; Total logic elements               ; 1,211                                       ;
;     Total combinational functions  ; 1,206                                       ;
;     Dedicated logic registers      ; 45                                          ;
; Total registers                    ; 45                                          ;
; Total pins                         ; 13                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0                                           ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 0                                           ;
; UFM blocks                         ; 0                                           ;
; ADC blocks                         ; 0                                           ;
+------------------------------------+---------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                                                    ;
+------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                           ; Setting                               ; Default Value                         ;
+------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                           ; 10M08SAU169C8G                        ;                                       ;
; Top-level entity name                                            ; Kap10_SiebensegmentVierstelligZaehler ; Kap10_SiebensegmentVierstelligZaehler ;
; Family name                                                      ; MAX 10                                ; Cyclone V                             ;
; Maximum processors allowed for parallel compilation              ; 2                                     ;                                       ;
; Use smart compilation                                            ; Off                                   ; Off                                   ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On                                    ; On                                    ;
; Enable compact report table                                      ; Off                                   ; Off                                   ;
; Restructure Multiplexers                                         ; Auto                                  ; Auto                                  ;
; Create Debugging Nodes for IP Cores                              ; Off                                   ; Off                                   ;
; Preserve fewer node names                                        ; On                                    ; On                                    ;
; Intel FPGA IP Evaluation Mode                                    ; Enable                                ; Enable                                ;
; Verilog Version                                                  ; Verilog_2001                          ; Verilog_2001                          ;
; VHDL Version                                                     ; VHDL_1993                             ; VHDL_1993                             ;
; State Machine Processing                                         ; Auto                                  ; Auto                                  ;
; Safe State Machine                                               ; Off                                   ; Off                                   ;
; Extract Verilog State Machines                                   ; On                                    ; On                                    ;
; Extract VHDL State Machines                                      ; On                                    ; On                                    ;
; Ignore Verilog initial constructs                                ; Off                                   ; Off                                   ;
; Iteration limit for constant Verilog loops                       ; 5000                                  ; 5000                                  ;
; Iteration limit for non-constant Verilog loops                   ; 250                                   ; 250                                   ;
; Add Pass-Through Logic to Inferred RAMs                          ; On                                    ; On                                    ;
; Infer RAMs from Raw Logic                                        ; On                                    ; On                                    ;
; Parallel Synthesis                                               ; On                                    ; On                                    ;
; DSP Block Balancing                                              ; Auto                                  ; Auto                                  ;
; NOT Gate Push-Back                                               ; On                                    ; On                                    ;
; Power-Up Don't Care                                              ; On                                    ; On                                    ;
; Remove Redundant Logic Cells                                     ; Off                                   ; Off                                   ;
; Remove Duplicate Registers                                       ; On                                    ; On                                    ;
; Ignore CARRY Buffers                                             ; Off                                   ; Off                                   ;
; Ignore CASCADE Buffers                                           ; Off                                   ; Off                                   ;
; Ignore GLOBAL Buffers                                            ; Off                                   ; Off                                   ;
; Ignore ROW GLOBAL Buffers                                        ; Off                                   ; Off                                   ;
; Ignore LCELL Buffers                                             ; Off                                   ; Off                                   ;
; Ignore SOFT Buffers                                              ; On                                    ; On                                    ;
; Limit AHDL Integers to 32 Bits                                   ; Off                                   ; Off                                   ;
; Optimization Technique                                           ; Balanced                              ; Balanced                              ;
; Carry Chain Length                                               ; 70                                    ; 70                                    ;
; Auto Carry Chains                                                ; On                                    ; On                                    ;
; Auto Open-Drain Pins                                             ; On                                    ; On                                    ;
; Perform WYSIWYG Primitive Resynthesis                            ; Off                                   ; Off                                   ;
; Auto ROM Replacement                                             ; On                                    ; On                                    ;
; Auto RAM Replacement                                             ; On                                    ; On                                    ;
; Auto DSP Block Replacement                                       ; On                                    ; On                                    ;
; Auto Shift Register Replacement                                  ; Auto                                  ; Auto                                  ;
; Allow Shift Register Merging across Hierarchies                  ; Auto                                  ; Auto                                  ;
; Auto Clock Enable Replacement                                    ; On                                    ; On                                    ;
; Strict RAM Replacement                                           ; Off                                   ; Off                                   ;
; Allow Synchronous Control Signals                                ; On                                    ; On                                    ;
; Force Use of Synchronous Clear Signals                           ; Off                                   ; Off                                   ;
; Auto RAM Block Balancing                                         ; On                                    ; On                                    ;
; Auto RAM to Logic Cell Conversion                                ; Off                                   ; Off                                   ;
; Auto Resource Sharing                                            ; Off                                   ; Off                                   ;
; Allow Any RAM Size For Recognition                               ; Off                                   ; Off                                   ;
; Allow Any ROM Size For Recognition                               ; Off                                   ; Off                                   ;
; Allow Any Shift Register Size For Recognition                    ; Off                                   ; Off                                   ;
; Use LogicLock Constraints during Resource Balancing              ; On                                    ; On                                    ;
; Ignore translate_off and synthesis_off directives                ; Off                                   ; Off                                   ;
; Timing-Driven Synthesis                                          ; On                                    ; On                                    ;
; Report Parameter Settings                                        ; On                                    ; On                                    ;
; Report Source Assignments                                        ; On                                    ; On                                    ;
; Report Connectivity Checks                                       ; On                                    ; On                                    ;
; Ignore Maximum Fan-Out Assignments                               ; Off                                   ; Off                                   ;
; Synchronization Register Chain Length                            ; 2                                     ; 2                                     ;
; Power Optimization During Synthesis                              ; Normal compilation                    ; Normal compilation                    ;
; HDL message level                                                ; Level2                                ; Level2                                ;
; Suppress Register Optimization Related Messages                  ; Off                                   ; Off                                   ;
; Number of Removed Registers Reported in Synthesis Report         ; 5000                                  ; 5000                                  ;
; Number of Swept Nodes Reported in Synthesis Report               ; 5000                                  ; 5000                                  ;
; Number of Inverted Registers Reported in Synthesis Report        ; 100                                   ; 100                                   ;
; Clock MUX Protection                                             ; On                                    ; On                                    ;
; Auto Gated Clock Conversion                                      ; Off                                   ; Off                                   ;
; Block Design Naming                                              ; Auto                                  ; Auto                                  ;
; SDC constraint protection                                        ; Off                                   ; Off                                   ;
; Synthesis Effort                                                 ; Auto                                  ; Auto                                  ;
; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                                    ; On                                    ;
; Pre-Mapping Resynthesis Optimization                             ; Off                                   ; Off                                   ;
; Analysis & Synthesis Message Level                               ; Medium                                ; Medium                                ;
; Disable Register Merging Across Hierarchies                      ; Auto                                  ; Auto                                  ;
; Resource Aware Inference For Block RAM                           ; On                                    ; On                                    ;
+------------------------------------------------------------------+---------------------------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                     ;
+-------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path          ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                                                        ; Library ;
+-------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------------------------------------+---------+
; Kap10_SiebensegmentVierstelligZaehler.vhd ; yes             ; User VHDL File               ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd ;         ;
; lpm_divide.tdf                            ; yes             ; Megafunction                 ; c:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_divide.tdf                                               ;         ;
; abs_divider.inc                           ; yes             ; Megafunction                 ; c:/intelfpga_lite/18.1/quartus/libraries/megafunctions/abs_divider.inc                                              ;         ;
; sign_div_unsign.inc                       ; yes             ; Megafunction                 ; c:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sign_div_unsign.inc                                          ;         ;
; aglobal181.inc                            ; yes             ; Megafunction                 ; c:/intelfpga_lite/18.1/quartus/libraries/megafunctions/aglobal181.inc                                               ;         ;
; db/lpm_divide_anl.tdf                     ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/lpm_divide_anl.tdf                     ;         ;
; db/sign_div_unsign_9nh.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/sign_div_unsign_9nh.tdf                ;         ;
; db/alt_u_div_ske.tdf                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_ske.tdf                      ;         ;
; db/add_sub_t3c.tdf                        ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/add_sub_t3c.tdf                        ;         ;
; db/add_sub_u3c.tdf                        ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/add_sub_u3c.tdf                        ;         ;
; db/lpm_divide_mtl.tdf                     ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/lpm_divide_mtl.tdf                     ;         ;
; db/sign_div_unsign_olh.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/sign_div_unsign_olh.tdf                ;         ;
; db/alt_u_div_qhe.tdf                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_qhe.tdf                      ;         ;
; db/lpm_divide_ptl.tdf                     ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/lpm_divide_ptl.tdf                     ;         ;
; db/sign_div_unsign_rlh.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/sign_div_unsign_rlh.tdf                ;         ;
; db/alt_u_div_0ie.tdf                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_0ie.tdf                      ;         ;
; db/lpm_divide_3vl.tdf                     ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/lpm_divide_3vl.tdf                     ;         ;
; db/sign_div_unsign_5nh.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/sign_div_unsign_5nh.tdf                ;         ;
; db/alt_u_div_kke.tdf                      ; yes             ; Auto-Generated Megafunction  ; C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_kke.tdf                      ;         ;
+-------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                                                                ;
+---------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                                                        ;
+---------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 1,211                                                                                                                        ;
;                                             ;                                                                                                                              ;
; Total combinational functions               ; 1206                                                                                                                         ;
; Logic element usage by number of LUT inputs ;                                                                                                                              ;
;     -- 4 input functions                    ; 263                                                                                                                          ;
;     -- 3 input functions                    ; 340                                                                                                                          ;
;     -- <=2 input functions                  ; 603                                                                                                                          ;
;                                             ;                                                                                                                              ;
; Logic elements by mode                      ;                                                                                                                              ;
;     -- normal mode                          ; 814                                                                                                                          ;
;     -- arithmetic mode                      ; 392                                                                                                                          ;
;                                             ;                                                                                                                              ;
; Total registers                             ; 45                                                                                                                           ;
;     -- Dedicated logic registers            ; 45                                                                                                                           ;
;     -- I/O registers                        ; 0                                                                                                                            ;
;                                             ;                                                                                                                              ;
; I/O pins                                    ; 13                                                                                                                           ;
;                                             ;                                                                                                                              ;
; Embedded Multiplier 9-bit elements          ; 0                                                                                                                            ;
;                                             ;                                                                                                                              ;
; Maximum fan-out node                        ; lpm_divide:Mod2|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|add_sub_11_result_int[12]~22 ;
; Maximum fan-out                             ; 36                                                                                                                           ;
; Total fan-out                               ; 3301                                                                                                                         ;
; Average fan-out                             ; 2.58                                                                                                                         ;
+---------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                         ;
+----------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+----------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+--------------+
; Compilation Hierarchy Node             ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name                                                                                                                    ; Entity Name                           ; Library Name ;
+----------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+----------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+--------------+
; |Kap10_SiebensegmentVierstelligZaehler ; 1206 (106)          ; 45 (45)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 13   ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler                                                                                                 ; Kap10_SiebensegmentVierstelligZaehler ; work         ;
;    |lpm_divide:Div0|                   ; 134 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div0                                                                                 ; lpm_divide                            ; work         ;
;       |lpm_divide_mtl:auto_generated|  ; 134 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div0|lpm_divide_mtl:auto_generated                                                   ; lpm_divide_mtl                        ; work         ;
;          |sign_div_unsign_olh:divider| ; 134 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div0|lpm_divide_mtl:auto_generated|sign_div_unsign_olh:divider                       ; sign_div_unsign_olh                   ; work         ;
;             |alt_u_div_qhe:divider|    ; 134 (134)           ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div0|lpm_divide_mtl:auto_generated|sign_div_unsign_olh:divider|alt_u_div_qhe:divider ; alt_u_div_qhe                         ; work         ;
;    |lpm_divide:Div1|                   ; 157 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div1                                                                                 ; lpm_divide                            ; work         ;
;       |lpm_divide_ptl:auto_generated|  ; 157 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div1|lpm_divide_ptl:auto_generated                                                   ; lpm_divide_ptl                        ; work         ;
;          |sign_div_unsign_rlh:divider| ; 157 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div1|lpm_divide_ptl:auto_generated|sign_div_unsign_rlh:divider                       ; sign_div_unsign_rlh                   ; work         ;
;             |alt_u_div_0ie:divider|    ; 157 (157)           ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div1|lpm_divide_ptl:auto_generated|sign_div_unsign_rlh:divider|alt_u_div_0ie:divider ; alt_u_div_0ie                         ; work         ;
;    |lpm_divide:Div2|                   ; 123 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div2                                                                                 ; lpm_divide                            ; work         ;
;       |lpm_divide_3vl:auto_generated|  ; 123 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div2|lpm_divide_3vl:auto_generated                                                   ; lpm_divide_3vl                        ; work         ;
;          |sign_div_unsign_5nh:divider| ; 123 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div2|lpm_divide_3vl:auto_generated|sign_div_unsign_5nh:divider                       ; sign_div_unsign_5nh                   ; work         ;
;             |alt_u_div_kke:divider|    ; 123 (123)           ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Div2|lpm_divide_3vl:auto_generated|sign_div_unsign_5nh:divider|alt_u_div_kke:divider ; alt_u_div_kke                         ; work         ;
;    |lpm_divide:Mod0|                   ; 273 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod0                                                                                 ; lpm_divide                            ; work         ;
;       |lpm_divide_anl:auto_generated|  ; 273 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod0|lpm_divide_anl:auto_generated                                                   ; lpm_divide_anl                        ; work         ;
;          |sign_div_unsign_9nh:divider| ; 273 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod0|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider                       ; sign_div_unsign_9nh                   ; work         ;
;             |alt_u_div_ske:divider|    ; 273 (273)           ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod0|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider ; alt_u_div_ske                         ; work         ;
;    |lpm_divide:Mod1|                   ; 226 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod1                                                                                 ; lpm_divide                            ; work         ;
;       |lpm_divide_anl:auto_generated|  ; 226 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod1|lpm_divide_anl:auto_generated                                                   ; lpm_divide_anl                        ; work         ;
;          |sign_div_unsign_9nh:divider| ; 226 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod1|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider                       ; sign_div_unsign_9nh                   ; work         ;
;             |alt_u_div_ske:divider|    ; 226 (226)           ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod1|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider ; alt_u_div_ske                         ; work         ;
;    |lpm_divide:Mod2|                   ; 150 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod2                                                                                 ; lpm_divide                            ; work         ;
;       |lpm_divide_anl:auto_generated|  ; 150 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod2|lpm_divide_anl:auto_generated                                                   ; lpm_divide_anl                        ; work         ;
;          |sign_div_unsign_9nh:divider| ; 150 (0)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod2|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider                       ; sign_div_unsign_9nh                   ; work         ;
;             |alt_u_div_ske:divider|    ; 150 (150)           ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod2|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider ; alt_u_div_ske                         ; work         ;
;    |lpm_divide:Mod3|                   ; 37 (0)              ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod3                                                                                 ; lpm_divide                            ; work         ;
;       |lpm_divide_anl:auto_generated|  ; 37 (0)              ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod3|lpm_divide_anl:auto_generated                                                   ; lpm_divide_anl                        ; work         ;
;          |sign_div_unsign_9nh:divider| ; 37 (0)              ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod3|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider                       ; sign_div_unsign_9nh                   ; work         ;
;             |alt_u_div_ske:divider|    ; 37 (37)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |Kap10_SiebensegmentVierstelligZaehler|lpm_divide:Mod3|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider ; alt_u_div_ske                         ; work         ;
+----------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+----------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 45    ;
; Number of registers using Synchronous Clear  ; 14    ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; dig_reg[0]                             ; 3       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+
; 41:1               ; 7 bits    ; 189 LEs       ; 182 LEs              ; 7 LEs                  ; Yes        ; |Kap10_SiebensegmentVierstelligZaehler|SSeg[3]~reg0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |Kap10_SiebensegmentVierstelligZaehler ;
+----------------+----------+---------------------------------------------------------------------------+
; Parameter Name ; Value    ; Type                                                                      ;
+----------------+----------+---------------------------------------------------------------------------+
; CLK_Freq       ; 12000000 ; Signed Integer                                                            ;
; MUX_Freq       ; 100      ; Signed Integer                                                            ;
+----------------+----------+---------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Mod0 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 14             ; Untyped                ;
; LPM_WIDTHD             ; 14             ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_anl ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Div0 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 14             ; Untyped                ;
; LPM_WIDTHD             ; 4              ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_mtl ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Mod1 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 14             ; Untyped                ;
; LPM_WIDTHD             ; 14             ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_anl ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Div1 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 14             ; Untyped                ;
; LPM_WIDTHD             ; 7              ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_ptl ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Mod2 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 14             ; Untyped                ;
; LPM_WIDTHD             ; 14             ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_anl ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Div2 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 14             ; Untyped                ;
; LPM_WIDTHD             ; 10             ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_3vl ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Mod3 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 14             ; Untyped                ;
; LPM_WIDTHD             ; 14             ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_anl ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 13                          ;
; cycloneiii_ff         ; 45                          ;
;     ENA               ; 11                          ;
;     ENA SLD           ; 4                           ;
;     SCLR              ; 14                          ;
;     plain             ; 16                          ;
; cycloneiii_lcell_comb ; 1206                        ;
;     arith             ; 392                         ;
;         1 data inputs ; 14                          ;
;         2 data inputs ; 66                          ;
;         3 data inputs ; 312                         ;
;     normal            ; 814                         ;
;         0 data inputs ; 50                          ;
;         1 data inputs ; 14                          ;
;         2 data inputs ; 459                         ;
;         3 data inputs ; 28                          ;
;         4 data inputs ; 263                         ;
;                       ;                             ;
; Max LUT depth         ; 34.20                       ;
; Average LUT depth     ; 27.24                       ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:05     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Processing started: Tue Nov 29 15:01:57 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Kap10_SiebensegmentVierstelligZaehler -c Kap10_SiebensegmentVierstelligZaehler
Info (20032): Parallel compilation is enabled and will use up to 2 processors
Info (12021): Found 2 design units, including 1 entities, in source file kap10_siebensegmentvierstelligzaehler.vhd
    Info (12022): Found design unit 1: Kap10_SiebensegmentVierstelligZaehler-rtl File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 18
    Info (12023): Found entity 1: Kap10_SiebensegmentVierstelligZaehler File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 5
Info (12127): Elaborating entity "Kap10_SiebensegmentVierstelligZaehler" for the top level hierarchy
Info (278001): Inferred 7 megafunctions from design logic
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod0" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 43
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div0" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 46
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod1" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 46
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div1" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 49
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod2" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 49
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div2" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 52
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod3" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 52
Info (12130): Elaborated megafunction instantiation "lpm_divide:Mod0" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 43
Info (12133): Instantiated megafunction "lpm_divide:Mod0" with the following parameter: File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 43
    Info (12134): Parameter "LPM_WIDTHN" = "14"
    Info (12134): Parameter "LPM_WIDTHD" = "14"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_anl.tdf
    Info (12023): Found entity 1: lpm_divide_anl File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/lpm_divide_anl.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9nh.tdf
    Info (12023): Found entity 1: sign_div_unsign_9nh File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/sign_div_unsign_9nh.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_ske.tdf
    Info (12023): Found entity 1: alt_u_div_ske File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_ske.tdf Line: 26
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_t3c.tdf
    Info (12023): Found entity 1: add_sub_t3c File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/add_sub_t3c.tdf Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_u3c.tdf
    Info (12023): Found entity 1: add_sub_u3c File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/add_sub_u3c.tdf Line: 22
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div0" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 46
Info (12133): Instantiated megafunction "lpm_divide:Div0" with the following parameter: File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 46
    Info (12134): Parameter "LPM_WIDTHN" = "14"
    Info (12134): Parameter "LPM_WIDTHD" = "4"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_mtl.tdf
    Info (12023): Found entity 1: lpm_divide_mtl File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/lpm_divide_mtl.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf
    Info (12023): Found entity 1: sign_div_unsign_olh File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/sign_div_unsign_olh.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_qhe.tdf
    Info (12023): Found entity 1: alt_u_div_qhe File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_qhe.tdf Line: 26
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div1" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 49
Info (12133): Instantiated megafunction "lpm_divide:Div1" with the following parameter: File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 49
    Info (12134): Parameter "LPM_WIDTHN" = "14"
    Info (12134): Parameter "LPM_WIDTHD" = "7"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_ptl.tdf
    Info (12023): Found entity 1: lpm_divide_ptl File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/lpm_divide_ptl.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_rlh.tdf
    Info (12023): Found entity 1: sign_div_unsign_rlh File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/sign_div_unsign_rlh.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_0ie.tdf
    Info (12023): Found entity 1: alt_u_div_0ie File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_0ie.tdf Line: 26
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div2" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 52
Info (12133): Instantiated megafunction "lpm_divide:Div2" with the following parameter: File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/Kap10_SiebensegmentVierstelligZaehler.vhd Line: 52
    Info (12134): Parameter "LPM_WIDTHN" = "14"
    Info (12134): Parameter "LPM_WIDTHD" = "10"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_3vl.tdf
    Info (12023): Found entity 1: lpm_divide_3vl File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/lpm_divide_3vl.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_5nh.tdf
    Info (12023): Found entity 1: sign_div_unsign_5nh File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/sign_div_unsign_5nh.tdf Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_kke.tdf
    Info (12023): Found entity 1: alt_u_div_kke File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_kke.tdf Line: 26
Info (286030): Timing-Driven Synthesis is running
Info (17016): Found the following redundant logic cells in design
    Info (17048): Logic cell "lpm_divide:Mod1|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|add_sub_7_result_int[0]~16" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_ske.tdf Line: 81
    Info (17048): Logic cell "lpm_divide:Mod1|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|add_sub_12_result_int[0]~26" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_ske.tdf Line: 46
    Info (17048): Logic cell "lpm_divide:Mod2|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|add_sub_13_result_int[0]~0" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_ske.tdf Line: 51
    Info (17048): Logic cell "lpm_divide:Mod2|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|op_12~18"
    Info (17048): Logic cell "lpm_divide:Mod2|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|add_sub_10_result_int[0]~22" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_ske.tdf Line: 36
    Info (17048): Logic cell "lpm_divide:Mod2|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|add_sub_11_result_int[0]~24" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_ske.tdf Line: 41
    Info (17048): Logic cell "lpm_divide:Mod2|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|add_sub_12_result_int[0]~26" File: C:/Users/Schmullus/VHDPlus/Projects/Kap10_SiebensegmentVierstelligZaehler/db/alt_u_div_ske.tdf Line: 46
    Info (17048): Logic cell "lpm_divide:Mod3|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|op_4~0"
    Info (17048): Logic cell "lpm_divide:Mod3|lpm_divide_anl:auto_generated|sign_div_unsign_9nh:divider|alt_u_div_ske:divider|op_3~18"
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 1224 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 2 input pins
    Info (21059): Implemented 11 output pins
    Info (21061): Implemented 1211 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 4823 megabytes
    Info: Processing ended: Tue Nov 29 15:02:33 2022
    Info: Elapsed time: 00:00:36
    Info: Total CPU time (on all processors): 00:00:36


