241: Vectors LDR PC, Reset_Addr 0x00000000 E59FF019 LDR PC,[PC,#0x0019] 242: LDR PC, Undef_Addr 0x00000004 E59FF019 LDR PC,[PC,#0x0019] 243: LDR PC, SWI_Addr 0x00000008 E59FF019 LDR PC,[PC,#0x0019] 244: LDR PC, PAbt_Addr 0x0000000C E59FF019 LDR PC,[PC,#0x0019] 245: LDR PC, DAbt_Addr 0x00000010 E59FF019 LDR PC,[PC,#0x0019] 246: NOP ; Reserved Vector 0x00000014 E1A00001 MOV R0,R1 247: LDR PC, IRQ_Addr 0x00000018 E51FFFF1 LDR PC,[PC,#-0x0FF1] 248: LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr 0x0000001C E59FF019 LDR PC,[PC,#0x0019] 249: LDR PC, FIQ_Addr 250: 251: Reset_Addr DCD Reset_Handler 252: Undef_Addr DCD Undef_Handler 253: SWI_Addr DCD SWI_Handler 254: PAbt_Addr DCD PAbt_Handler 255: DAbt_Addr DCD DAbt_Handler 256: DCD 0 ; Reserved Address 257: IRQ_Addr DCD IRQ_Handler 258: FIQ_Addr DCD FIQ_Handler 259: 260: ;/ Modifikation: Code an Adresse 0x40 springt zum Reset_Handler 261: ;/ Adresse 0x40 wird bei leerem Boot-Block als erster ausfuehrbarer 262: ;/ Befehl im internen Flash erreicht 0x00000020 80000059 ANDHI R0,R0,R9,ASR R0 0x00000024 80000041 DD 0x80000041 0x00000028 80000045 DD 0x80000045 0x0000002C 80000049 DD 0x80000049 0x00000030 8000004D DD 0x8000004D 0x00000034 00000001 DD 0x00000001 0x00000038 80000051 DD 0x80000051 0x0000003C 80000055 DD 0x80000055 0x00000040 0000005C DD 0x0000005C 263: B Reset_Handler 0x00000044 EA000005 B Reset_Handler(0x00000060) 264: Undef_Handler B Undef_Handler 0x00000048 EAFFFFFE B 0x00000048 265: SWI_Handler B SWI_Handler 0x0000004C EAFFFFFE B 0x0000004C 266: PAbt_Handler B PAbt_Handler 0x00000050 EAFFFFFE B 0x00000050 267: DAbt_Handler B DAbt_Handler 0x00000054 EAFFFFFE B 0x00000054 268: IRQ_Handler B IRQ_Handler 0x00000058 EAFFFFFE B 0x00000058 269: FIQ_Handler B FIQ_Handler 0x0000005C EAFFFFFE B 0x0000005C 322: LDR R0, =VPBDIV 0x00000060 E59F00B8 LDR R0,[PC,#0x00B8] 323: LDR R1, =VPBDIV_Val 0x00000064 E3A01001 MOV R1,#0x00000001 324: STR R1, [R0] 325: ENDIF 326: 327: 328: ; Setup PLL 329: IF PLL_SETUP <> 0 0x00000068 E5801000 STR R1,[R0] 330: LDR R0, =PLL_BASE 0x0000006C E59F00B0 LDR R0,[PC,#0x00B0] 331: MOV R1, #0xAA 0x00000070 E3A010AA MOV R1,#0x000000AA 332: MOV R2, #0x55 333: 334: ; Configure and Enable PLL 0x00000074 E3A02055 MOV R2,#0x00000055 335: MOV R3, #PLLCFG_Val 0x00000078 E3A03024 MOV R3,#0x00000024 336: STR R3, [R0, #PLLCFG_OFS] 0x0000007C E5803004 STR R3,[R0,#0x0004] 337: MOV R3, #PLLCON_PLLE 0x00000080 E3A03001 MOV R3,#0x00000001 338: STR R3, [R0, #PLLCON_OFS] 0x00000084 E5803000 STR R3,[R0] 339: STR R1, [R0, #PLLFEED_OFS] 0x00000088 E580100C STR R1,[R0,#0x000C] 340: STR R2, [R0, #PLLFEED_OFS] 341: 342: ; Wait until PLL Locked 0x0000008C E580200C STR R2,[R0,#0x000C] 343: PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] 0x00000090 E5903008 LDR R3,[R0,#0x0008] 344: ANDS R3, R3, #PLLSTAT_PLOCK 0x00000094 E2133B01 ANDS R3,R3,#0x00000400 345: BEQ PLL_Loop 346: 347: ; Switch to PLL Clock 0x00000098 0AFFFFFC BEQ 0x00000090 348: MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) 0x0000009C E3A03003 MOV R3,#0x00000003 349: STR R3, [R0, #PLLCON_OFS] 0x000000A0 E5803000 STR R3,[R0] 350: STR R1, [R0, #PLLFEED_OFS] 0x000000A4 E580100C STR R1,[R0,#0x000C] 351: STR R2, [R0, #PLLFEED_OFS] 352: ENDIF ; PLL_SETUP 353: 354: 355: ; Setup MAM 356: IF MAM_SETUP <> 0 0x000000A8 E580200C STR R2,[R0,#0x000C] 357: LDR R0, =MAM_BASE 0x000000AC E59F0074 LDR R0,[PC,#0x0074] 358: MOV R1, #MAMTIM_Val 0x000000B0 E3A01004 MOV R1,#0x00000004 359: STR R1, [R0, #MAMTIM_OFS] 0x000000B4 E5801004 STR R1,[R0,#0x0004] 360: MOV R1, #MAMCR_Val 0x000000B8 E3A01002 MOV R1,#0x00000002 361: STR R1, [R0, #MAMCR_OFS] 362: ENDIF ; MAM_SETUP 363: 364: 365: ; Memory Mapping (when Interrupt Vectors are in RAM) 366: MEMMAP EQU 0xE01FC040 ; Memory Mapping Control 367: IF :DEF:REMAP 0x000000BC E5801000 STR R1,[R0] 368: LDR R0, =MEMMAP 369: IF :DEF:EXTMEM_MODE 370: MOV R1, #3 371: ELIF :DEF:RAM_MODE 372: MOV R1, #2 373: ELSE 0x000000C0 E59F0064 LDR R0,[PC,#0x0064] 374: MOV R1, #1 375: ENDIF 0x000000C4 E3A01001 MOV R1,#0x00000001 376: STR R1, [R0] 377: ENDIF 378: 379: 380: ; Initialise Interrupt System 381: ; ... 382: 383: 384: ; Setup Stack for each mode 385: 0x000000C8 E5801000 STR R1,[R0] 386: LDR R0, =Stack_Top 387: 388: ; Enter Undefined Instruction Mode and set its Stack Pointer 0x000000CC E59F005C LDR R0,[PC,#0x005C] 389: MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit 0x000000D0 E321F0DB MSR CPSR_c,#0x000000DB 390: MOV SP, R0 0x000000D4 E1A0D000 MOV R13,R0 391: SUB R0, R0, #UND_Stack_Size 392: 393: ; Enter Abort Mode and set its Stack Pointer 0x000000D8 E2400000 SUB R0,R0,#0x00000000 394: MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit 0x000000DC E321F0D7 MSR CPSR_c,#0x000000D7 395: MOV SP, R0 0x000000E0 E1A0D000 MOV R13,R0 396: SUB R0, R0, #ABT_Stack_Size 397: 398: ; Enter FIQ Mode and set its Stack Pointer 0x000000E4 E2400000 SUB R0,R0,#0x00000000 399: MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit 0x000000E8 E321F0D1 MSR CPSR_c,#0x000000D1 400: MOV SP, R0 0x000000EC E1A0D000 MOV R13,R0 401: SUB R0, R0, #FIQ_Stack_Size 402: 403: ; Enter IRQ Mode and set its Stack Pointer 0x000000F0 E2400000 SUB R0,R0,#0x00000000 404: MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit 0x000000F4 E321F0D2 MSR CPSR_c,#0x000000D2 405: MOV SP, R0 0x000000F8 E1A0D000 MOV R13,R0 406: SUB R0, R0, #IRQ_Stack_Size 407: 408: ; Enter Supervisor Mode and set its Stack Pointer 0x000000FC E2400080 SUB R0,R0,#0x00000080 409: MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit 0x00000100 E321F0D3 MSR CPSR_c,#0x000000D3 410: MOV SP, R0 0x00000104 E1A0D000 MOV R13,R0 411: SUB R0, R0, #SVC_Stack_Size 412: 413: ; Enter User Mode and set its Stack Pointer 0x00000108 E2400008 SUB R0,R0,#0x00000008 414: MSR CPSR_c, #Mode_USR 415: IF :DEF:__MICROLIB 416: 417: EXPORT __initial_sp 418: 419: ELSE 420: 0x0000010C E321F010 MSR CPSR_c,#0x00000010 421: MOV SP, R0 0x00000110 E1A0D000 MOV R13,R0 422: SUB SL, SP, #USR_Stack_Size 423: 424: ENDIF 425: 426: 427: ; Enter the C code 428: 429: IMPORT __main 0x00000114 E24DAB01 SUB R10,R13,#0x00000400 430: LDR R0, =__main 0x00000118 E59F0014 LDR R0,[PC,#0x0014] 431: BX R0 432: 433: 434: IF :DEF:__MICROLIB 435: 436: EXPORT __heap_base 437: EXPORT __heap_limit 438: 439: ELSE 440: ; User Initial Stack & Heap 441: AREA |.text|, CODE, READONLY 442: 443: IMPORT __use_two_region_memory 444: EXPORT __user_initial_stackheap 445: __user_initial_stackheap 446: