library ieee;
use ieee.std_logic_1164.all;

entity taktteiler is
port
(
    clk50   : in std_logic;     -- IO17 clock 50MHz
    phi2    : in std_logic;     -- PHI2 clock 1.77MHz
    --
    phi2short : out std_logic   -- PHI2 shorted clock 1.77MHz
);
end entity taktteiler;

architecture rtl of taktteiler is

    signal temp1    : std_logic;
    signal temp2    : std_logic;
    signal counter  : integer := 0;

begin

    process(clk50)
    begin
        if rising_edge(clk50) then
            if phi2 = '1' then
                temp1 <= '1';
            else
                temp1 <= '0';
            end if;

            temp2 <= '1';
            if counter >= 9 then
                counter <= 0;
                temp2   <= '0';
            else
                counter <= counter + 1;
            end if;
        end if;
   end process;

   phi2short <= temp1 and temp2;

end architecture rtl;