Place & Route TRACE Report
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Lattice TRACE Report - Setup, Version ispLever_v72_PROD_Build (44)
Wed Dec 02 16:17:37 2009
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Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce.exe -v 1 -o receiver_dpram.twr receiver_dpram.ncd receiver_dpram.prf
Design file: receiver_dpram.ncd
Preference file: receiver_dpram.prf
Device,speed: LCMXO2280C,3
Report level: verbose report, limited to 1 item per preference
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Preference Summary
FREQUENCY PORT "RXC" 80.000000 MHz (0 errors) 918 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "RXC" 80.000000 MHz ;
918 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.860ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RECEIVE_CONTROL/wr_adr_i_4 (from RXC_c -)
Destination: FF Unknown RAM_B/mem_0_0/RAM1 (to RXC_c +)
Delay: 4.764ns (20.7% logic, 79.3% route), 2 logic levels.
Constraint Details:
4.764ns physical path delay RECEIVE_CONTROL/SLICE_12 to RAM_B/mem_0_0/SLICE_24 meets
6.250ns delay constraint less
0.000ns skew and
0.626ns WREN_SET requirement (totaling 5.624ns) by 0.860ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.613 R10C10C.CLK to R10C10C.Q0 RECEIVE_CONTROL/SLICE_12 (from RXC_c)
ROUTE 5 2.117 R10C10C.Q0 to R10C11A.D1 RECEIVE_CONTROL/wr_adr_i_4
CTOF_DEL --- 0.371 R10C11A.D1 to R10C11A.F1 SLICE_57
ROUTE 4 1.663 R10C11A.F1 to R9C8B.LSR RAM_B/dec0_wre3 (to RXC_c)
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4.764 (20.7% logic, 79.3% route), 2 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
4.968ns 55.PADDI to R10C10C.CLK
Destination Clock :
Delay Connection
4.968ns 55.PADDI to R9C8B.CLK2
Report: 92.764MHz is the maximum frequency for this preference.
Report Summary
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Preference | Constraint| Actual|Levels
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| | |
FREQUENCY PORT "RXC" 80.000000 MHz ; | 80.000 MHz| 92.764 MHz| 2
| | |
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All preferences were met.
Clock Domains Analysis
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Found 1 clocks:
Clock Domain: RXC_c Source: RXC.PAD Loads: 46
Covered under: FREQUENCY PORT "RXC" 80.000000 MHz ;
Timing summary:
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Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 918 paths, 1 nets, and 476 connections (77.3% coverage)
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Generated from the file 'C:\ispTOOLS7_2_STRT\work\i2s_ip_25_receiver_v2\receiver_dpram.twr'